c_1000.vhd

交流电压表相应的VHDL代码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity c_1000 is
  port(clk:in std_logic;
        co:out std_logic);
end  c_1000;

architecture rtl of c_1000 is
  signal s:std_logic_vector(8 downto 0);
  signal a:std_logic;
begin
  co<=a;
  process(clk)
   begin
    if(clk'event and clk='1') then
     if(s="111110011") then
       s<="000000000";
       a<=not a;
     else
       s<=s+1; 
     end if;
    end if;
  end process;
end  rtl;