代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/309740/13665051
txt addbcd_4.txt
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity eecadd_4 is
port( a: in std_logic_vector(3 downto 0);
b: in std_logic_vector(
www.eeworm.com/read/309740/13665053
txt addbcd_8.txt
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity eecadd_8 is
port (cin8:in std_logic;
a:in std_logic_vector(7 downto 0);
www.eeworm.com/read/309739/13665137
vho fft.vho
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation
www.eeworm.com/read/309713/13665829
vhd eecadd_4.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity eecadd_4 is
port( a: in std_logic_vector(3 downto 0);
b: in std_logic_vector(
www.eeworm.com/read/308159/13706872
vhd dff89.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY dff89 IS
PORT( clk : IN STD_LOGIC;
clear : IN STD_LOGIC;
Din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
Dout : OUT STD_LOGIC_VECTO
www.eeworm.com/read/308159/13706876
vhd dff15.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY dff15 IS
PORT( clk : IN STD_LOGIC;
clear : IN STD_LOGIC;
Din : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
Dout : OUT STD_LOGIC_VECT
www.eeworm.com/read/308159/13707028
vhd dff8.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY dff8 IS
PORT( clk : IN STD_LOGIC;
clear : IN STD_LOGIC;
Din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
Dout : OUT STD_LOGIC_V
www.eeworm.com/read/307761/13715437
txt qichewendengvhdlsheji.txt
0571-86919140
汽车尾灯VHDL设计
标签/分类：
1．系统设计要求
用6个发光管模拟6个汽车尾灯（左右各3个），用4个开关作为汽车控制信号,分别为：左拐、右拐、故障和刹车。
车匀速行驶时，6个汽车尾灯全灭；右拐时，车右边3个尾灯从左至右顺序亮灭；左拐时，车左边3个尾灯从右至左顺序亮灭；故障时车6个尾灯一起明灭闪烁；刹车时，6个尾灯全亮
...
www.eeworm.com/read/307606/13719515
vhd fourbitsuber.vhd
--------------------------------------------------------------------------------------------------------------------
--实验题号 : Ex2-3
--项目名称 : 4bit减法器
--文件名 : FourBitSuber.vhd
--作者 : 田
www.eeworm.com/read/307202/13726875
vhd lcd.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity lcd is
Port ( clk : in std_logic; --3.125MHZ FROM div16 Module