代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/324371/13267032
vhd topclock.vhd
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity topclock is
Port(
clk,reset,set:in std_logic; ---系统时钟、复位、时间设置信号
www.eeworm.com/read/324371/13267064
bak topclock.vhd.bak
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity topclock is
Port(clk,reset,set:in std_logic;
S1,m1,h1:in std_logic_vector(1 down
www.eeworm.com/read/324083/13288831
txt 新建 文本文档.txt
library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity PL_MFSK is
port(clk :in std_logic; --系统时钟
start :in std
www.eeworm.com/read/238890/13316011
txt smj_etester.txt
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY smj_etester IS
PORT (BCLK:IN STD_LOGIC;
TCLK:IN STD_LOGIC;
CLR:IN STD_LOGIC;
CL:I
www.eeworm.com/read/323754/13323130
dat wave24.dat
$WAVE4TIMED
$RESOLUTION 1000
I 1 "e#9#std_logicc9 UX01ZWLH-"
$OUT 1 1 do
$IN 5 1 res
$IN 9 1 cs
$IN +4 1 clk
$IN +4 1 di
I 2 "a#28#std_logic_vector(7 downto 0)1 ricd7 0 e#9#std_logicc9 UX01ZWL
www.eeworm.com/read/323754/13323252
dat wave22.dat
$WAVE4TIMED
$RESOLUTION 1000
I 1 "e#9#std_logicc9 UX01ZWLH-"
$OUT 1 1 do
$IN 5 1 res
$IN 9 1 cs
$IN +4 1 clk
$IN +4 1 di
I 2 "a#28#std_logic_vector(7 downto 0)1 ricd7 0 e#9#std_logicc9 UX01ZWL
www.eeworm.com/read/323754/13323356
dat wave26.dat
$WAVE4TIMED
$RESOLUTION 1000
I 1 "e#9#std_logicc9 UX01ZWLH-"
$IN 1 1 clk
$IN 5 1 cs
I 2 "a#29#std_logic_vector(11 downto 0)1 ricd11 0 e#9#std_logicc9 UX01ZWLH-"
$BUS S 57 2 12 current_state
$SC
www.eeworm.com/read/323754/13323358
dat wave0.dat
$WAVE4TIMED
$RESOLUTION 1000
I 1 "e#9#std_logicc9 UX01ZWLH-"
$OUT 1 1 do
$IN 5 1 res
$IN 9 1 cs
$IN +4 1 clk
$IN +4 1 di
$ENDTIME 10000000
$WAVES 1
=0 T 0
=1 D 0 1
$VALUES
V 2
U
1
$END
www.eeworm.com/read/137409/13323660
vhd wave2.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ab is
port ( CLK,CLR: IN STD_LOGIC;
DD : in std_logic_vector(1 downto 0);
LD :
www.eeworm.com/read/137361/13326683
vhd multi8x8.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
ENTITY MULTI8X8 IS -- 8位乘法器顶层设计
PORT ( P1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);