代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/440264/7691328
vhd reg.vhd
-- reg.vhd
-- This module implements a 16-bit general purpose register. The contents of
-- register is loaded on the rising edge of "clk". It is cleared to zero when
-- "reset" is asserted low. T
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vhd pc.vhd
-- pc.vhd
-- This module implements the 16-bit program Counter (PC). PC is loaded from
-- PCIn on the next clock when "PCControl" is asserted high. PC is cleared to
-- zero when "reset" is assert
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vhd cfg_regs.vhd
--*****************************************************************************
-- FILE : PCI_CFGREG
-- DATE : 1.9.1999
-- REVISION: 1.1
-- DESIGNER: KA
-- Descr : PCI Configuration Space
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vhd pcit_core.vhd
--*****************************************************************************
-- DESIGN : PCI Target Core
-- FILE : PCIT_CORE.vhd
-- DATE : 1.9.1999
-- REVISION: 1.1
-- DESIGNER: KA
--
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vhd ball.vhd
--乒乓球灯模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ball is
port(clk:in std_logic;--乒乓球灯前进时钟
clr:in std_logic;--乒乓球灯清零
way:in std_logic;--乒乓球灯前进方向
en
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vhd cnt24.vhd
LIBRARY IEEE; -- 24进制计数器
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT24 IS
PORT ( CLK,EN, U_D : IN STD_LOGIC;
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vhd planeagc.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for ins
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vhd openlock.vhd
library ieee;
use ieee.std_logic_1164.all;
entity openlock is
port( clk : in std_logic;
change : in std_logic;
test : in std_logic;
code0 : in std_logic_vector(3 downto 0);
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vhd bcdconvtb.vhd
--
-- Copyright (C) Doulos Ltd 2001
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use STD.textio.all;
entity BCDConvTB is
end;
architecture Bench of BCDConvTB is
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vhd bcdconv.vhd
--
-- Copyright (C) Doulos Ltd 2001
--
library IEEE;
use IEEE.std_logic_1164.all;
entity BCDConv is
generic (N : positive); -- number of digits
port (Clock : in std_logic;