pc.vhd

设计一个非常简单的16位CPU

-- pc.vhd

-- This module implements the 16-bit program Counter (PC). PC is loaded from
-- PCIn on the next clock when "PCControl" is asserted high. PC is cleared to
-- zero when "reset" is asserted low. The output of PC is driven onto "PCOut".

-- Inputs: 
--    PCIn      - 16-bit data to be input into PC when control signal is asserted
--    PCControl - 1-bit control signal. 
--    reset     - 1-bit reset signal which clears PC to zero when it is asserted low
--    clk       - 1-bit clock signal for PC

-- Outputs: 
--    PCOut     - 16-bit counter output

-- Author:    Easyright
-- E-mail:    [e-mail]
-- Date:      17-08-2003
-- Copyright: http://www.EasyRight.net

------------------------------------------------------------------------------------------------------ 

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity pc is
  port (
    PCIn:       in std_logic_vector(15 downto 0);
    PCControl:  in std_logic;
    reset:      in std_logic;
    clk:        in std_logic;
    PCOut:      out std_logic_vector(15 downto 0)
  );
end pc;

architecture arc_pc of pc is
  signal t: std_logic_vector(15 downto 0);
begin
  PCOut <= t;
  process(clk, reset)
  begin
    if (reset = '0') then
      t <= "0000000000000000"; 
    elsif rising_edge(clk) then
      if (PCControl = '1') then 
        t <= PCIn; 
      else
        t <= t; 
      end if;
    end if;
  end process; 
end arc_pc;