代码搜索:std

找到约 10,000 项符合「std」的源代码

代码结果 10,000
www.eeworm.com/read/442712/7646188

vhd hsata.vhd

--------------------------------------------------------------------------- --------------------------------------------------------------------------- -- -- Copyright (C) 2004 Free Model Foundry; ht
www.eeworm.com/read/442712/7646190

vhd dsata.vhd

--------------------------------------------------------------------------- --------------------------------------------------------------------------- -- -- Copyright (C) 2004 Free Model Foundry; ht
www.eeworm.com/read/441728/7666361

vhd cnt_12.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY cnt_12 IS PORT(CLK :IN STD_LOGIC; reset :IN STD_LOGIC; en :IN STD_LOGIC; co:OUT STD_ULOGIC;
www.eeworm.com/read/441728/7666362

bak cnt_12.vhd.bak

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY cnt_12 IS PORT(CLK :IN STD_LOGIC; reset :IN STD_LOGIC; en :IN STD_LOGIC; co:OUT STD_ULOGIC;
www.eeworm.com/read/441728/7666369

bak cnt_10.vhd.bak

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY cnt_10 IS PORT(CLK :IN STD_LOGIC; reset :IN STD_LOGIC; en :IN STD_LOGIC; co:OUT STD_ULOGIC;
www.eeworm.com/read/441728/7666375

bak cnt_60.vhd.bak

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY cnt_60 IS PORT(CLK :IN STD_LOGIC; reset :IN STD_LOGIC; en :IN STD_LOGIC; co:OUT STD_ULOGIC;
www.eeworm.com/read/441728/7666377

vhd cnt_60.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY cnt_60 IS PORT(CLK :IN STD_LOGIC; reset :IN STD_LOGIC; en :IN STD_LOGIC; co:OUT STD_ULOGIC;
www.eeworm.com/read/441728/7666382

vhd cnt_10.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY cnt_10 IS PORT(CLK :IN STD_LOGIC; reset :IN STD_LOGIC; en :IN STD_LOGIC; co:OUT STD_ULOGIC;
www.eeworm.com/read/441060/7676635

vhd cpu1.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith; use ieee.std_logic_signed.all; use ieee.numeric_std.all; entity cpu1 is port(clk:in std_logic; rst:in std_logic
www.eeworm.com/read/440808/7680614

vhd video.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; --------------------**********************************************----------------------- ENTITY VIDEO IS PORT(