video.vhd

来自「显示总线扩展的_VHDL代码」· VHDL 代码 · 共 42 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

--------------------**********************************************-----------------------
ENTITY VIDEO IS
   PORT(
       	DISPLAYA: OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
		DISPLAYB: OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
		DISPLAYC: OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
		DISPLAYD: OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
		DISPLAYE: OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
		DISPLAYF: OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
		ADDRESS:  IN  STD_LOGIC_VECTOR(2 DOWNTO 0);
		CLK:	  IN  STD_LOGIC;
		DATAIN:   IN  STD_LOGIC_VECTOR(6 DOWNTO 0)
        );
END VIDEO;

ARCHITECTURE Control OF VIDEO IS
-------------------------------------------------------------------------
BEGIN
-----------------------------------------------------------------------------------	
	PROCESS(DATAIN,ADDRESS,CLK)
	BEGIN
		IF(CLK'EVENT AND CLK='1')THEN
		    IF(ADDRESS="000") THEN
			    DISPLAYA<=DATAIN;
			ELSIF(ADDRESS="001")THEN
				DISPLAYB<=DATAIN;
			ELSIF(ADDRESS="010")THEN
				DISPLAYC<=DATAIN;
			ELSIF(ADDRESS="011")THEN
				DISPLAYD<=DATAIN;
			ELSIF(ADDRESS="100")THEN
				DISPLAYE<=DATAIN;
			ELSIF(ADDRESS="101")THEN
				DISPLAYF<=DATAIN;
			END IF;
		END IF;
	END PROCESS;
END Control;