cpu1.vhd

自己刚写的一个RISC的cpu

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith;
use ieee.std_logic_signed.all;
use ieee.numeric_std.all;

entity cpu1 is
       port(clk:in std_logic;
            rst:in std_logic;
            memout:in std_logic_vector(15 downto 0);
            ram_in:in std_logic;
            result:out std_logic;
            alu_result:out std_logic;
            re:out std_logic;
            wr:out std_logic;
            pc_address:out std_logic_vector(15 downto 0)
            );
end cpu1;

architecture one of cpu1 is
       signal     instr      :std_logic_vector(15 downto 0);
       signal     muxalu1_c  :std_logic;                      
       signal     muxalu2_c  :std_logic;                       --
       signal     alu_c      :std_logic_vector(1 downto 0);   
       signal     muxwrd_c   :std_logic_vector(1 downto 0);   
       signal     en_ir      :std_logic;                      
       signal     en_wr      :std_logic;                       
       signal     en_r1      :std_logic;                       
       signal     en_r2      :std_logic;                       -- 
       signal     wra        :std_logic_vector(1 downto 0);   
       signal     rra1       :std_logic_vector(1 downto 0);   
       signal     rra2       :std_logic_vector(1 downto 0);    
       signal     comp_c     :std_logic_vector(2 downto 0);   
       signal     pcalu_c    :std_logic_vector(2 downto 0);    
       signal     jmp_imm    :std_logic_vector(11 downto 0);  
       signal     comp_imm   :std_logic_vector(7 downto 0);    
       signal     rdm_imm    :std_logic_vector(9 downto 0); 
       signal     pc_imm     : std_logic_vector(15 downto 0) ;  
       signal     muxwrd_mov :std_logic;
       signal     muxalu1_rs :std_logic;
       signal     muxalu1_rt :std_logic;
       signal     muxalu1_out:std_logic;
       --signal     muxalu2_rs :std_logic;
       --signal     muxalu2_rt :std_logic;
       signal     muxalu2_out:std_logic;
       signal     muxwrd_alu :std_logic;
       signal     muxwrd_out :std_logic;
       signal     comp_out   :std_logic;
       signal     pcalu_out  :std_logic_vector(15 downto 0);
       
       component control
       port(clk        :in std_logic;
            rst        :in std_logic;
            instr      :in std_logic_vector(15 downto 0); 
            re         :out std_logic;                       
            wr         :out std_logic;                      
            muxalu1_c  :out std_logic;                      
            muxalu2_c  :out std_logic;                       
            alu_c      :out std_logic_vector(1 downto 0);    
            muxwrd_c   :out std_logic_vector(1 downto 0);   
            en_ir      :out std_logic;                      
            en_wr      :out std_logic;                      
            en_r1      :out std_logic;                      
            en_r2      :out std_logic;                       
            wra        :out std_logic_vector(1 downto 0);    
            rra1       :out std_logic_vector(1 downto 0);    
            rra2       :out std_logic_vector(1 downto 0);  
            comp_c     :out std_logic_vector(2 downto 0);  
            pcalu_c    :out std_logic_vector(2 downto 0);   
            jmp_imm    :out std_logic_vector(11 downto 0);   
            comp_imm   :out std_logic_vector(7 downto 0);    
            rdm_imm    :out std_logic_vector(9 downto 0);    
            muxwrd_mov :out std_logic                       
            );
       end component; 
       
       
       component ir
           port(memout  :in std_logic_vector(15 downto 0);
                clk     :in std_logic;
                rst     :in std_logic;
                en_ir   :in std_logic;
                instr   :out std_logic_vector(15 downto 0)
                );
       end component;
       
       component muxalu1
           port(muxalu1_c   :in std_logic;
                muxalu1_rs  :in std_logic;
                --muxalu1_rt  :in std_logic;
                muxalu1_out :out std_logic
                );
       end component;   
       
       component muxalu2
           port(muxalu2_c   :in std_logic;
                --muxalu2_rs  :in std_logic;
                muxalu2_rt  :in std_logic;
                muxalu2_out :out std_logic
                );
       end component;  
       
       component alu
           port(alu_c  :in std_logic_vector(1 downto 0);
                aluin1 :in std_logic;
                aluin2 :in std_logic;
                aluout :out std_logic 
                );
       end component; 
       
       component muxwrd 
           port(muxwrd_c    :in std_logic_vector(1 downto 0);
                muxwrd_alu  :in std_logic;
                muxwrd_mov  :in std_logic;
                muxwrd_rdm  :in std_logic;
                muxwrd_out  :out std_logic
                );
       end component;
       
       component regfile
           port(clk     :in std_logic;
                reset   :in std_logic;
                en_wr   :in std_logic;---write enable
                en_r1   :in std_logic;---set 1 enable
                en_r2   :in std_logic;---set 2 enbale
                wra     :in std_logic_vector(1 downto 0);---wrtie address
                wrd     :in std_logic;------write data
                rra1    :in std_logic_vector(1 downto 0); ----read address 1
                rra2    :in std_logic_vector(1 downto 0);------read address 2
                rsd     :out std_logic;-----read data
                rtd     :out std_logic
               );
       end component;
       
       component compare
            port(comp_c    :in std_logic_vector(2 downto 0);
                 comp_in1  :in std_logic;
                 comp_in2  :in std_logic;
                 comp_out  :out std_logic
              );
      end component;
       
       component pcalu
           port(pcalu_c    :in std_logic_vector(2 downto 0);
                pc_imm     :in std_logic_vector(15 downto 0);
                jmp_imm    :in std_logic_vector(11 downto 0);
                comp_imm   :in std_logic_vector(7 downto 0);
                rdm_imm    :in std_logic_vector(9 downto 0);
                comp_out   :in std_logic;
                pcalu_out  :out std_logic_vector(15 downto 0)
              );
       end component;
       
       component pc
           port(clk    :in std_logic;
                rst    :in std_logic;
                pc_in  :in std_logic_vector(15 downto 0);
                pc_out :out std_logic_vector(15 downto 0));
       end component;
       
       begin
             result<=muxwrd_out;
             alu_result<=muxwrd_alu;
              pc_address<=pc_imm;
         U1: control
             port map(clk =>clk,
                       rst =>rst,
                       instr(15 downto 0)=>instr(15 downto 0),
                       re  =>re,                      
                       wr  =>wr,                     
                       muxalu1_c  =>muxalu1_c,                     
                       muxalu2_c  =>muxalu2_c,                       
                       alu_c(1 downto 0)=>alu_c(1 downto 0),  
                       muxwrd_c(1 downto 0)=>muxwrd_c(1 downto 0), 
                       en_ir =>en_ir,                     
                       en_wr =>en_wr,                      
                       en_r1 =>en_r1,                      
                       en_r2 =>en_r2,                       
                       wra(1 downto 0)=>wra(1 downto 0),    
                       rra1(1 downto 0)=>rra1(1 downto 0),
                       rra2(1 downto 0)=>rra2(1 downto 0),
                       comp_c(2 downto 0)=>comp_c(2 downto 0),
                       pcalu_c(2 downto 0)=>pcalu_c(2 downto 0),
                       jmp_imm(11 downto 0)=>jmp_imm(11 downto 0),
                       comp_imm(7 downto 0)=>comp_imm(7 downto 0),   
                       rdm_imm(9 downto 0)=>rdm_imm(9 downto 0),   
                       muxwrd_mov=>muxwrd_mov                       
                      );
         
         U2: ir   
             port map(memout(15 downto 0)=>memout(15 downto 0),
                      clk =>clk,
                      rst =>rst,
                      en_ir=>en_ir,
                      instr(15 downto 0)=>instr(15 downto 0)
                     ); 
                        
         U3: muxalu1
             port map(muxalu1_c=>muxalu1_c,
                      muxalu1_rs=>muxalu1_rs,
                      --muxalu1_rt=>muxalu1_rt,
                      muxalu1_out=>muxalu1_out
                      );
          
         U4: muxalu2
             port map(muxalu2_c=>muxalu2_c,
                      --muxalu2_rs=>muxalu1_rs,
                      muxalu2_rt=>muxalu1_rt,
                      muxalu2_out=>muxalu2_out
                      ); 
         U5: alu
             port map(alu_c(1 downto 0)=>alu_c(1 downto 0), 
                      aluin1 =>muxalu1_out,
                      aluin2 =>muxalu2_out,
                      aluout =>muxwrd_alu 
                      --aluout =>alu_result
                      );
         
         U6: muxwrd 
             port map(muxwrd_c(1 downto 0)=>muxwrd_c(1 downto 0),
                      muxwrd_alu=>muxwrd_alu,
                      muxwrd_mov=>muxwrd_mov,
                      muxwrd_rdm=>ram_in,
                      muxwrd_out=>muxwrd_out
                      );
         U7: regfile
             port map(clk =>clk,
                      reset=>rst,
                      en_wr=>en_wr,
                      en_r1=>en_r1,
                      en_r2=>en_r2,
                      wra=>wra,
                      wrd =>muxwrd_out,
                      rra1=>rra1,
                      rra2=>rra2,
                      rsd=>muxalu1_rs,
                      rtd=>muxalu1_rt
                     );
         U8: compare
             port map(comp_c(2 downto 0)=>comp_c(2 downto 0),
                      comp_in1=>muxalu1_rs,
                      comp_in2=>muxalu1_rt,
                      comp_out=>comp_out
                     );
                    
         U9: pcalu
             port map(pcalu_c(2 downto 0)=>pcalu_c(2 downto 0),
                      pc_imm (15 downto 0)=>pc_imm(15 downto 0),
                      jmp_imm(11 downto 0)=>jmp_imm(11 downto 0),
                      comp_imm(7 downto 0)=>comp_imm(7 downto 0),
                      rdm_imm (9 downto 0)=>rdm_imm(9 downto 0),
                      comp_out=>comp_out,
                      pcalu_out(15 downto 0)=>pcalu_out(15 downto 0)
                      );                                  
           
         U10:pc
             port map(clk =>clk,
                      rst =>rst,
                      pc_in(15 downto 0)=>pcalu_out(15 downto 0),
                      --pc_out(15 downto 0)=>pc_address(15 downto 0),
                      pc_out(15 downto 0)=>pc_imm(15 downto 0)
                      );
         
 end one;