代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/449295/7509160
vhd fifo_tb.vhd
--********************************************************************
--* This automatically generated Test Bench template has been created*
--* By ACTIVE-HDL . Copyright (C) ALDEC
www.eeworm.com/read/447464/7550662
vhd uart_clock.vhd
--
-- KCPSM3 reference design - Real Time Clock with UART communications
--
-- Ken Chapman - Xilinx Ltd - October 2003
--
-- The design demonstrates the following:-
-- Connection of KC
www.eeworm.com/read/444247/7615950
vhd display.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity display is
port(disclk:in std_logic;
num1:in std_logic_vector(3 downto 0);
num2:in std_logic_vector(3
www.eeworm.com/read/444242/7616162
vhd display.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity display is
port(disclk:in std_logic;
num1:in std_logic_vector(3 downto 0);
num2:in std_logic_vector(3
www.eeworm.com/read/444137/7617669
vhd crcgen.vhd
library IEEE;
use IEEE.std_logic_1164.all;
entity CRCGEN is
port(
SD :in std_logic;
CLRN :in std_logic;
SFT :in std_logic;
CRC :out std_logic_vector(7 downto 0);
clk :in
www.eeworm.com/read/443723/7624739
vhd ide.vhd
--------------------------------------------------------------------
-- Company : XESS Corp.
-- Engineer : Dave Vanden Bout
-- Creation Date : 01/30/2006
-- Copyright : 2006, XESS C
www.eeworm.com/read/443658/7629297
vhd cannon.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity cannon is
Port ( clk : in std_logic;
reset : in std_logic;
www.eeworm.com/read/443658/7629301
vhd top.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity top is
Port ( sysclk : in std_logic;
resn : in std_logic;
www.eeworm.com/read/443250/7635476
vhd v5_2.vhd
library ieee;
use ieee.std_logic_1164.all;
entity V5_2 is
port(sel : in std_logic_vector(2 downto 0);
a : in std_logic;
b : in std_logic;
c : in std_logic;
www.eeworm.com/read/443250/7635479
vhd v5_5.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity V5_5 is
port(a : in std_logic_vector(3 downto 0);
clk : in std_logic;
rst : in std_logi