crcgen.vhd

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library IEEE;
use IEEE.std_logic_1164.all;

entity CRCGEN is

	port(
		SD		:in std_logic;
		CLRN	:in	std_logic;
		SFT		:in std_logic;

		CRC		:out std_logic_vector(7 downto 0);

		clk		:in std_logic;
		rstn	:in std_logic
	);
end CRCGEN;


architecture MAIN of CRCGEN is
signal CRCbuf	:std_logic_vector(7 downto 0);
begin
	process(clk,rstn)begin
		if(rstn='0')then
			CRCbuf<=(others=>'0');
		elsif(clk='1' and clk' event)then
			if(CLRN='0')then
				CRCbuf<=(others=>'0');
			elsif(SFT='1')then
				CRCbuf(6 downto 0)<=CRCbuf(7 downto 1);
				CRCbuf(7)<=CRCbuf(0) xor SD;
			end if;
		end if;
	end process;
	CRC<=CRCbuf;
end MAIN;