代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/462742/7196633
vhd dds.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity dds is
port(k: in std_logic_vector(31 downto 0);
n: in std_logic_vector(31 downto 0);
clk:in
www.eeworm.com/read/462646/7198775
vhd filter.vhd
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:52:40 11/27/08
-- Design Name:
-- Module Name: Filter -
www.eeworm.com/read/462646/7198864
vhd registro.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity registro is
Generic ( tam : integer :=8);
Port ( inbus : in std_logic_vec
www.eeworm.com/read/462646/7198885
vhd sim1.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.numeric_std.ALL;
USE ieee.math_real.ALL;
ENTITY sim1_vhd IS
END sim1_vhd;
ARCHITECTURE behavior OF s
www.eeworm.com/read/462482/7200948
vhd cnt_12.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY cnt_12 IS
PORT(CLK :IN STD_LOGIC;
reset :IN STD_LOGIC;
en :IN STD_LOGIC;
co:OUT STD_ULOGIC;
www.eeworm.com/read/462482/7200949
bak cnt_12.vhd.bak
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY cnt_12 IS
PORT(CLK :IN STD_LOGIC;
reset :IN STD_LOGIC;
en :IN STD_LOGIC;
co:OUT STD_ULOGIC;
www.eeworm.com/read/462482/7200956
bak cnt_10.vhd.bak
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY cnt_10 IS
PORT(CLK :IN STD_LOGIC;
reset :IN STD_LOGIC;
en :IN STD_LOGIC;
co:OUT STD_ULOGIC;
www.eeworm.com/read/462482/7200962
bak cnt_60.vhd.bak
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY cnt_60 IS
PORT(CLK :IN STD_LOGIC;
reset :IN STD_LOGIC;
en :IN STD_LOGIC;
co:OUT STD_ULOGIC;
www.eeworm.com/read/462482/7200964
vhd cnt_60.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY cnt_60 IS
PORT(CLK :IN STD_LOGIC;
reset :IN STD_LOGIC;
en :IN STD_LOGIC;
co:OUT STD_ULOGIC;
www.eeworm.com/read/462482/7200969
vhd cnt_10.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY cnt_10 IS
PORT(CLK :IN STD_LOGIC;
reset :IN STD_LOGIC;
en :IN STD_LOGIC;
co:OUT STD_ULOGIC;