dds.vhd

利用EDA硬件描述语言来实现DDS功能

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity dds is
   port(k: in std_logic_vector(31 downto 0);
        n: in std_logic_vector(31 downto 0);
        clk:in std_logic;
        en:in std_logic;
        reset:in std_logic;
         p:out std_logic_vector(31 downto 0));
end entity dds;
architecture art  of dds is
component sum32 is
  port(k: in std_logic_vector(31 downto 0);
        clk:in std_logic;
        en:in std_logic;
        reset:in std_logic;
         out1:out std_logic_vector(31 downto 0));
end component sum32;
component reg1 is
port(d: in std_logic_vector(31 downto 0);
        clk:in std_logic;
        q:out std_logic_vector(31 downto 0));
end component reg1;
component adder32 is
port(a: in std_logic_vector(31 downto 0);
        n: in std_logic_vector(31 downto 0);
        clk:in std_logic;
        en:in std_logic;
        out2:out std_logic_vector(31 downto 0));
end component adder32;
component reg2 is
port(e: in std_logic_vector(31 downto 0);
      clk:in std_logic;
      p:out std_logic_vector(31 downto 0));
end component reg2;
signal s1:std_logic_vector(31 downto 0);
signal s2:std_logic_vector(31 downto 0);
signal s3:std_logic_vector(31 downto 0);
begin
u0:sum32 port map(k=>k,en=>en,reset=>reset,clk=>clk,out1=>s1);
u1:reg1 port map(d=>s1,clk=>clk,q=>s2);
u2:adder32 port map(a=>s2,en=>en,clk=>clk,n=>n,out2=>s3);
u3:reg2 port map(e=>s3,clk=>clk,p=>p);
end architecture art;