sim1.vhd

This sources implement a 8-bit FIR Filter with selectable coefficent rom.

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.numeric_std.ALL;
USE ieee.math_real.ALL;

ENTITY sim1_vhd IS				
END sim1_vhd;

ARCHITECTURE behavior OF sim1_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT filtro_fir_mac
	PORT(
		entrada : IN std_logic_vector(7 downto 0);
		reset : IN std_logic;
		clk : IN std_logic;
		enable : in std_logic;
		sel : in std_logic_vector(1 downto 0);          
		salida : OUT std_logic_vector(22 downto 0)
		);
	END COMPONENT;

	--Inputs
	SIGNAL reset :  std_logic := '1';
	SIGNAL clk :  std_logic := '0';
	SIGNAL entrada :  std_logic_vector(7 downto 0) := (others=>'0');
	SIGNAL x1,x2,x,i : real:=0.0;
	signal sel : std_logic_vector(1 downto 0) := (others=>'0');
	signal enable: std_logic := '1';

	--Outputs
	SIGNAL salida :  std_logic_vector(22 downto 0);
	CONSTANT periodo: time := 20 ns;

BEGIN
	-- Instantiate the Unit Under Test (UUT)
	uut: filtro_fir_mac PORT MAP(
		entrada => entrada,
		salida => salida,
		reset => reset,
		clk => clk,
		enable => enable,
		sel => sel
	);
							  
	clk <= not clk after periodo/2;
	
	sino : PROCESS
	BEGIN			 	 
		while	true loop
			x1  <= 100.0*sin(2.0*MATH_PI*i/1000.0);
			x2  <= 10.0*sin(2.0*MATH_PI*i/100.0);
			x   <= x1 + x2;
			entrada<= std_logic_vector(to_signed(integer(x),8));
			i   <= i + 1.0;
			wait for periodo;
		end loop;		
	END PROCESS;

																					
	tb : PROCESS
	BEGIN
		-- Place stimulus here
		reset<='1';
		wait for periodo;
		reset<='0';
		wait for 999*periodo;
		reset<='1';
		wait for periodo;
		reset<='0';
		sel <= "01";
		wait for 999*periodo;
		sel <= "10";
		wait for 999*periodo;
		sel <= "11";
--		wait for 9*periodo;
--		entrada <= "00000001";
--		wait for 9*periodo;
--		entrada <= "00000001";
--		wait for 9*periodo;
--		entrada <= "00000001";
--		wait for 9*periodo;
--		entrada <= "00000001";
--		wait for 9*periodo;
--		entrada <= "00000001";
--		wait for 9*periodo;
--		entrada <= "00000000";
		wait; -- will wait forever
	END PROCESS;

END;