filter.vhd

来自「This sources implement a 8-bit FIR Filte」· VHDL 代码 · 共 38 行

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-- Company: 
-- Engineer:
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-- Create Date:    12:52:40 11/27/08
-- Design Name:    
-- Module Name:    Filter - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
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-- Dependencies:
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-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Filter is
	 Generic (  );
    Port ( in : in std_logic;
           out : out std_logic;
           clk : in std_logic);
end Filter;

architecture Behavioral of Filter is

	
begin


end Behavioral;