代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/104566/7146680
vhd mux2_1.vhd
--core_design
--mux2_1
--all right reserved
library ieee;
use ieee.std_logic_1164.all;
entity mux2_1 is
port (en:in std_logic;
in1:in std_logic_vector(31 downto 0);
in2:in std_logi
www.eeworm.com/read/328107/7153493
vhd dds.vhd
--DDS.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DDS IS
PORT(K:IN STD_LOGIC_VECTOR(9 DOWNTO 0);
EN:IN STD_LOGIC;
RESET:IN STD_LOGIC;
www.eeworm.com/read/328107/7153513
vhd sum99.vhd
--SUM910.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SUM99 IS
PORT(K: IN STD_LOGIC_VECTOR(9 DOWNTO 0);
CLK: IN STD_LOGIC;
EN: IN STD_L
www.eeworm.com/read/370001/7154617
vhd imagexlib_arch.vhd
--*******************************************************************
-- Copyright(C) 2005 by Xilinx, Inc. All rights reserved.
-- This text/file contains proprietary, confidential
-- information o
www.eeworm.com/read/464438/7158501
vhd songer.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY Songer IS -- 顶层设计
PORT ( clk : in std_logic;
CODE1 : OUT std_logic_vector(2 dow
www.eeworm.com/read/463246/7185261
vhd mux48.vhd
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
ENTITY MUX48 IS
PORT ( S : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
A1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
A2 : IN STD_LOGIC_V
www.eeworm.com/read/463246/7185361
vhd mux41s.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX41S IS
PORT (S1,S2 : IN STD_LOGIC ;
A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
www.eeworm.com/read/463246/7185373
vhd mux48.vhd
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
ENTITY MUX48 IS
PORT ( S : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
A1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
A2 : IN STD_LOGIC_V
www.eeworm.com/read/463246/7185494
vhd mux48.vhd
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
ENTITY MUX48 IS
PORT ( S : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
A1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
A2 : IN STD_LOGIC_V
www.eeworm.com/read/463246/7185646
vhd mux41s.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX41S IS
PORT (S1,S2 : IN STD_LOGIC ;
A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(7 DOWNTO 0);