代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/465817/7046457
vhd csla_32.vhd
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity
www.eeworm.com/read/464588/7065919
vhd top.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity top is
port(
TopClkMcu:in std_logic;
TopDada:in std_logic;
TopEn:in std_logic;
TopClkDds:in std_lo
www.eeworm.com/read/464588/7065922
vhd counter16.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter16 is
port(
CLR: in std_logic;
FIN: IN std_logic;
START: in std_logic;
Q: OUT
www.eeworm.com/read/464588/7065924
vhd counter.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
port(
CLR32: in std_logic;
FIN32: IN std_logic;
START32: in std_logic;
Q3
www.eeworm.com/read/464588/7065925
vhd topp.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity topp is
port(
toppRECCLK: in std_logic; --通信时钟
toppRECDATA: out std_logic;
www.eeworm.com/read/174386/7087976
vhd avr_core.vhd
--************************************************************************************************
-- Top entity for AVR core
-- Version 1.11
-- Designed by Ruslan Lepetenok
-- Modified 03.11.200
www.eeworm.com/read/174386/7087985
vhd ramdatareg.vhd
--**********************************************************************************************
-- RAM data register for the AVR Core
-- Version 0.1
-- Modified 02.11.2002
-- Designed by Ruslan Lepe
www.eeworm.com/read/369273/7099331
vhd shizhi.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SHIZHI IS
PORT(RST,DIAO: IN STD_LOGIC;
ZHUANG: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
SZ: OUT STD_LOGIC_VE
www.eeworm.com/read/369273/7099338
bak shizhi.vhd.bak
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SHIZHI IS
PORT(RST,DIAO: IN STD_LOGIC;
ZHUANG: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
SZ: OUT STD_LOGIC_VE
www.eeworm.com/read/369273/7099391
vhd shizhi.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SHIZHI IS
PORT(RST,DIAO: IN STD_LOGIC;
ZHUANG: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
SZ: OUT STD_LOGIC_VE