📄 csla_32.vhd
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----------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity CSLA_32 is generic (n : integer := 32; m : integer := 4); port ( a : in STD_LOGIC_VECTOR (31 downto 0); b : in STD_LOGIC_VECTOR (31 downto 0); ci : in STD_LOGIC; co : out STD_LOGIC; s : out STD_LOGIC_VECTOR (31 downto 0));end CSLA_32;architecture Behavioral of CSLA_32 is component CPA_4 port( a : in STD_LOGIC_VECTOR; b : in STD_LOGIC_VECTOR; ci : in STD_LOGIC; co : out STD_LOGIC; p : out STD_LOGIC; s : out STD_LOGIC_VECTOR); end component; component mux2_1 is generic( delay: TIME := 2 NS); port (x: IN STD_LOGIC; y: IN STD_LOGIC; s0: IN STD_LOGIC; z: OUT STD_LOGIC); end component; -- define 4bit 2to1 mux component mux4bit is generic (n : integer := m); Port ( i0 : in STD_LOGIC_VECTOR(n-1 downto 0); i1 : in STD_LOGIC_VECTOR(n-1 downto 0); s : in STD_LOGIC; o : out STD_LOGIC_VECTOR(n-1 downto 0)); end component; signal c0 : STD_LOGIC_VECTOR(n/m-1 downto 0); signal c1 : STD_LOGIC_VECTOR(n/m-1 downto 0); signal c : STD_LOGIC_VECTOR(n/m downto 0); signal s0 : STD_LOGIC_VECTOR(n-1 downto 0); signal s1 : STD_LOGIC_VECTOR(n-1 downto 0);begin c(0) <= ci; oGen : for i in 1 to n/m generate -- carry in = 0 oCPA4_0 : CPA_4 port map(a(i*m-1 downto (i-1)*m), b(i*m-1 downto (i-1)*m), '0', c0(i-1), open, s0(i*m-1 downto (i-1)*m)); -- carry in = 1 oCPA4_1 : CPA_4 port map(a(i*m-1 downto (i-1)*m), b(i*m-1 downto (i-1)*m), '1', c1(i-1), open, s1(i*m-1 downto (i-1)*m)); -- select the rigth sum oMux4bit1 : mux4bit port map(s0(i*m-1 downto (i-1)*m), s1(i*m-1 downto (i-1)*m), c(i-1),s(i*m-1 downto (i-1)*m)); -- select the rigth carry oMux2_1: mux2_1 port map(c0(i-1), c1(i-1), c(i-1), c(i)); end generate; co <= c(n/m); end Behavioral;
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