topp.vhd

低频数字相位测量仪仿真的软件部分

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity topp is
	port(
		toppRECCLK: in std_logic;	                             --通信时钟	
		toppRECDATA: out std_logic;								 --通信数据输出
		toppRECEN: in std_logic;								--通信使能
		toppADDRESS:in std_logic_vector(2 downto 0); 			--地址线，选择输出的数据
		toppimbark:in std_logic;	 							--装载信号
		toppclr:in std_logic; 									--清零信号
		toppfa:in std_logic;									--被侧信号
		toppfb:in std_logic; 
		toppTp:in std_logic;   									--单片机开启的闸门
		standclk:in std_logic	                        
		);
end topp;  	   

architecture behav of topp is	
signal toppTt:std_logic;   	
signal standdata:std_logic_vector(31 downto 0);	
signal fadata:std_logic_vector(15 downto 0);  
signal phasdata:std_logic_vector(31 downto 0);
signal phaseenbuf:std_logic;
component countrl is	   
	port(
		CLR: in std_logic;			
		Fa: IN std_logic;				
		Fb: in std_logic;
		Tp:in std_logic;	 
		Tt: buffer std_logic;
		phasen:out std_logic
		);
end component ;	   	

component counter is	   
	port(
		CLR32: in std_logic;			
		FIN32: IN std_logic;				
		START32: in std_logic;				
		Q32: OUT std_logic_vector(31 downto 0)
		);
end component ;		   

component  receive is 
		port(
		RECCLK: in std_logic;			
		RECDATA: out std_logic;				
		RECEN: in std_logic;		
		ADDRESS:in std_logic_vector(2 downto 0); 
		imbark:in std_logic;
		RECbuff0:in std_logic_vector(15 downto 0);
		RECbuff1:in std_logic_vector(15 downto 0);
		RECbuff2:in std_logic_vector(15 downto 0);
		RECbuff3:in std_logic_vector(15 downto 0);
		RECbuff4:in std_logic_vector(15 downto 0)

		);
end component ;		 

component  counter16 is   
	port(
		CLR: in std_logic;			
		FIN: IN std_logic;				
		START: in std_logic;				
		Q: OUT std_logic_vector(15 downto 0)
		);	 
end component ;

begin
	u1:countrl
	port map(
		CLR=>toppclr,			
		Fa=>toppfa,				
		Fb=>toppfb,
		Tp=>toppTp,	 
		Tt=>toppTt,
		phasen=>phaseenbuf
		);
		
	u2:counter              --
	port map( 
		CLR32=>toppclr,			
		FIN32=>standclk,				
		START32=>toppTt,				
		Q32=>standdata
		); 	
	u3:counter16           --测量频率
	port map( 
		CLR=>toppclr,			
		FIN=>toppfa,				
		START=>toppTt,				
		Q=>fadata
	);	
	u4:counter           --测量相位
	port map( 
		CLR32=>toppclr,			
		FIN32=>standclk,				
		START32=>phaseenbuf,		
		Q32=>phasdata
	);  
	u5:	receive
	port map (
		RECCLK=>toppRECCLK,			
		RECDATA=>toppRECDATA,			
		RECEN=>toppRECEN,		
		ADDRESS=>toppADDRESS,
		imbark=>toppimbark,
		RECbuff0=>phasdata(15 downto 0),
		RECbuff1=>phasdata(31 downto 16),
		RECbuff2=>fadata,
		RECbuff3=>standdata(15 downto 0),
		RECbuff4=>standdata(31 downto 16)	
		); 
		end;