代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/353811/10416392
vhd 加法器源程序.vhd
------------------------------------------------------------------------
-- Single-bit adder
------------------------------------------------------------------------
library IEEE;
use IEEE.std_log
www.eeworm.com/read/353811/10416398
txt 加法器描述.txt
-- A Variety of Adder Styles
-- download from: www.fpga.com.cn & www.pld.com.cn
------------------------------------------------------------------------
-- Single-bit adder
-----------------------
www.eeworm.com/read/353811/10416490
vhd 相应加法器的测试向量（test bench).vhd
-- download from: www.pld.com.cn & www.fpga.com.cn
entity testbench is
end;
------------------------------------------------------------------------
-- testbench for 8-bit adder
------------
www.eeworm.com/read/353706/10428967
vhd counter32b.vhd
LIBRARY IEEE; --32位计数器
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY COUNTER32B IS
PORT (FIN : IN STD_LOGIC; --时钟信号
CLR : IN STD_LOGIC;
www.eeworm.com/read/424337/10461727
vhd mux4_1.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY mux4_1 IS
PORT( i0,i1,i2,i3,a,b:IN STD_LOGIC;
q:OUT STD_LOGIC);
END mux4_1;
ARCHITECTURE be OF mux4_1 IS
SIGNAL sel:STD_LOG
www.eeworm.com/read/161016/10463592
vhd 相应加法器的测试向量（test bench).vhd
-- download from: www.pld.com.cn & www.fpga.com.cn
entity testbench is
end;
------------------------------------------------------------------------
-- testbench for 8-bit adder
------------
www.eeworm.com/read/160847/10486173
vhd 加法器源程序.vhd
------------------------------------------------------------------------
-- Single-bit adder
------------------------------------------------------------------------
library IEEE;
use IEEE.std_log
www.eeworm.com/read/160847/10486180
vhd 相应加法器的测试向量（test bench).vhd
-- download from: www.pld.com.cn & www.fpga.com.cn
entity testbench is
end;
------------------------------------------------------------------------
-- testbench for 8-bit adder
------------
www.eeworm.com/read/160657/10510653
vhd car.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY car IS
PORT(
iSensorState:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
CLRn,clkin:IN STD_LOGIC;
Dcl
www.eeworm.com/read/423934/10525652
vhd scan4digit.vhd
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:16:45 11/20/2008
-- Design Name:
-- Module Name: Scan4Digit