scan4digit.vhd

Scan 4 Digit VHDL code

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:16:45 11/20/2008 
-- Design Name: 
-- Module Name:    Scan4Digit - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Scan4Digit is
port( Digit0 : in std_logic_vector (6 downto 0);
Digit1 : in std_logic_vector(6 downto 0);
Digit2 : in std_logic_vector(6 downto 0);
Digit3 : in std_logic_vector(6 downto 0);
Clock : in std_logic;
An : out std_logic_vector(3 downto 0);
Ca : out std_logic;
Cb : out std_logic;
Cc : out std_logic;
Cd : out std_logic;
Ce : out std_logic;
Cf : out std_logic;
Cg : out std_logic;
Dp : out std_logic);
end Scan4Digit;

architecture Scan4Digit_Arch of Scan4Digit is
signal iCount16: std_logic_vector (15 downto 0) := (others=>'0');
 --signal iCount16: std_logic_vector (15 downto 14) :=(others=>'0');
   signal iDigitOut: std_logic_vector (6 downto 0);
begin

-- Generate the scan clock 50MHz/2**16 (763Hz)
process(Clock)
begin
if Clock'event and Clock='1' then
iCount16 <= iCount16 + '1';
end if;
end process;

--Send four digits to four 7-segment display using scan mode

with iCount16 (15 downto 14) select
iDigitOut <=Digit0 when "00", -- Connect Digit0 to the 7- segment display
Digit1 when "01", -- Connect Digit1 to the 7-segment display
Digit2 when "10", -- Connect Digit2 to the 7-segment display
Digit3 when "11", -- Connect Digit3 to the 7-segment display
Digit0 when others;

with iCount16 (15 downto 14) select
An <= "1110" when "00", -- with AN0 low only
"1101" when "01", -- with AN1 low only
"1011" when "10", -- with AN2 low only
"0111" when "11", -- with AN3 low only
"1110" when others;
Ca <= iDigitOut(6);
Cb <= iDigitOut(5);
Cc <= iDigitOut(4);
Cd <= iDigitOut(3);
Ce <= iDigitOut(2);
Cf <= iDigitOut(1);
Cg <= iDigitOut(0);
Dp <= '1';
end Scan4Digit_Arch;