mux4_1.vhd

来自「2位加法器」· VHDL 代码 · 共 26 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY mux4_1 IS
PORT( i0,i1,i2,i3,a,b:IN STD_LOGIC;
                    q:OUT STD_LOGIC);
END mux4_1;
ARCHITECTURE be OF mux4_1 IS
SIGNAL sel:STD_LOGIC_VECTOR(1 DOWNTO 0);  
 BEGIN  
 sel<=a&b;
  PROCESS(sel,i0,i1,i2,i3)
  begin

     IF sel ="00" THEN 
            q<=i0;
     ELSIF  sel ="01" THEN 
            q<=i1;
     ELSIF  sel ="10" THEN 
            q<=i2;
     ELSE
            q<=i3;
     END IF;
   END PROCESS;
END be;