代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/428603/8856517
vhd keywatch.vhd
library IEEE, unisim;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use unisim.vcomponents.all;
use work.key_Inter_pckg.all;
entity KeyWatch is --100_000
generic(FREQ : natural := 50000 );
www.eeworm.com/read/428603/8856544
vhd keytx.vhd
library IEEE, unisim;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use unisim.vcomponents.all;
use work.key_Inter_pckg.all;
entity KeyTx is --100_000
generic(FREQ : natural := 50000 );
www.eeworm.com/read/428603/8856553
vhd keyvga.vhd
library IEEE, unisim;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.key_Inter_pckg.all;
--library unisim;
--use unisim.
www.eeworm.com/read/428603/8856554
vhd topkbwatch.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TopKbWatch is
Port ( clk,ps2_data,ps2_clk : in STD_LOGIC;
SW7,SW6,SW5,SW
www.eeworm.com/read/186779/8910755
m stdcor.m
function [std_r]=stdcor(xindu,num)
warning off MATLAB:divideByZero;
if xindu>0.5
f_std=1./(finv(xindu,num-2,1));
else
f_std=finv(1-xindu,1,num-2);
end
std_r=sqrt(1./(1+(num-2)./f_std));
www.eeworm.com/read/284640/8912181
txt 加法器源程序.txt
------------------------------------------------------------------------
-- Single-bit adder
------------------------------------------------------------------------
library IEEE;
use IEEE.std_log
www.eeworm.com/read/284640/8912184
txt 相应加法器的测试向量（test bench).txt
-- download from: www.pld.com.cn & www.fpga.com.cn
entity testbench is
end;
------------------------------------------------------------------------
-- testbench for 8-bit adder
------------
www.eeworm.com/read/383870/8913452
vhd sha1_fa.vhd
------------------------------------------------------------------------
--
-- Single-bit adder
--
------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_
www.eeworm.com/read/383774/8919024
vhd componentslib.vhd
---------------------------------------------------------------------------
---------------------------------------------------------------------------
--组原 Group 6;
--顶层数据包
--将各个模块(ALU,Q_REG,RAM_
www.eeworm.com/read/383774/8919134
vhd ureg.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ureg is
port (
clk, reset, load: in std_logic;
d : in std_logic_vector(15 downto 0)