sha1_fa.vhd

来自「本算法基于leon2协处理器接口标准」· VHDL 代码 · 共 28 行

------------------------------------------------------------------------
--
-- Single-bit adder
--
------------------------------------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;

ENTITY sha1_fa IS
    PORT (
          a    : in std_logic;
          b    : in std_logic;
          cin  : in std_logic;
          sum  : out std_logic;
          cout : out std_logic
          );
END sha1_fa;


-- description of adder using concurrent signal assignments
ARCHITECTURE rtl OF sha1_fa IS
BEGIN
    sum <= (a xor b) xor cin;
    cout <= (a and b) or (cin and a) or (cin and b);
END rtl;