sha1_4fa_nocout_slice.vhd

来自「本算法基于leon2协处理器接口标准」· VHDL 代码 · 共 78 行

------------------------------------------------------------------------
--
-- sha1_4fa_slice without cout used in the wallace-tree
--
------------------------------------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;

ENTITY sha1_4fa_nocout_slice IS
    PORT (
          a       : IN  std_logic;
          b       : IN  std_logic;
          c       : IN  std_logic;
          d       : IN  std_logic;
          e       : IN  std_logic;
          f        : IN  std_logic;
          cin0    : IN  std_logic;
          cin1    : IN  std_logic;
          cin2    : IN  std_logic;
          sum    : OUT std_logic
          );
END sha1_4fa_nocout_slice;


-- description of adder using concurrent signal assignments
ARCHITECTURE rtl OF sha1_4fa_nocout_slice IS
     
    COMPONENT sha1_fa_nocout
    PORT (
          a    : in std_logic;
          b    : in std_logic;
          cin  : in std_logic;
          sum  : out std_logic
          );
    END COMPONENT;
     
    SIGNAL    sum0_internal    :  std_logic;
    SIGNAL    sum1_internal    :  std_logic;
    SIGNAL    sum2_internal    :  std_logic;
     
BEGIN

   ADDR1: sha1_fa_nocout
   PORT MAP(
      a    => a,
      b    => b,
      cin  => c,
      sum  => sum0_internal
      );
      
   ADDR2: sha1_fa_nocout
   PORT MAP(
      a    => sum0_internal,
      b    => d,
      cin  => e,
      sum  => sum1_internal
      );
    
   ADDR3: sha1_fa_nocout
   PORT MAP(
      a    => sum1_internal,
      b    => f,
      cin  => cin0,
      sum  => sum2_internal
      );  

   ADDR4: sha1_fa_nocout
   PORT MAP(
      a    => sum2_internal,
      b    => cin1,
      cin  => cin2,
      sum  => sum
      ); 

END rtl;