topkbwatch.vhd

many application on kit SP-3: VGA, digital clock, counter, interface PS2....

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity TopKbWatch is
    Port ( clk,ps2_data,ps2_clk : in  STD_LOGIC;
         SW7,SW6,SW5,SW4: in  STD_LOGIC;
			ledin0,ledin1,ledin2,ledin3,ledin4,ledin5 : out  STD_LOGIC_VECTOR (3 downto 0));
end TopKbWatch;

architecture Behavioral of  TopKbWatch is	
	component DongHo 
    Port ( clk,SW7,SW6,SW5,SW4 : in  std_logic;
				sccode  : in  std_logic_VECTOR (7 downto 0);
	        BCD0,BCD1,BCD2,BCD3,BCD4,BCD5:out std_logic_VECTOR (3 downto 0));
	end component;	
		
	component KeyWatch  
	  generic(FREQ : natural := 50000 );  
	  port(clk  : in  std_logic;    
			 rdy  : buffer  std_logic;  
			 ps2_clk : in  std_logic;          
			 ps2_data: in  std_logic;           
			 s       : out std_logic_vector(7 downto 0); 
			 sccode  : out std_logic_vector(7 downto 0));
	end component;
	component divclk_1hz is
    Port ( clk1 : in  STD_LOGIC;
           clk2 : out STD_LOGIC);
	end component;
	signal rdy,clk1: std_logic;
	signal s,sccode: STD_LOGIC_VECTOR (7 downto 0);
begin
	S1: divclk_1hz port map(clk,clk1);
	S2:DongHo port map(clk1,SW7,SW6,SW5,SW4,sccode,ledin0,ledin1,ledin2,ledin3,ledin4,ledin5);
	S10:keyWatch  port map(clk,rdy,ps2_clk,ps2_data,s,sccode);
	
end Behavioral;