ureg.vhd

来自「组成原理的大作业」· VHDL 代码 · 共 26 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ureg is 
port (
      clk, reset, load: in std_logic;
      d                : in std_logic_vector(15 downto 0); 
      q                : buffer std_logic_vector(15 downto 0));
end ureg;

architecture archureg of ureg is
begin 
      p1 : process (reset, clk )
         begin
               if reset='1' then
                   q <= (others=>'0');
               elsif (clk'event and clk='1') then
                  if load='1' then
                   q <= d;
                  else
                   q <= q;
                  end if;
               end if;
         end process;
end archureg;