代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/426972/8988371
vhd gh_fifo_async_rrd_sr.vhd
---------------------------------------------------------------------
-- Filename: gh_fifo_async_rrd_sr.vhd
--
--
-- Description:
-- an Asynchronous FIFO,
-- using "Style #2" gray code
www.eeworm.com/read/176855/9482095
vhw wgetinstr.vhw
-- F:\CPU
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Thu Oct 20 16:48:26 2005
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your Test Bench Waveform
-
www.eeworm.com/read/170129/9818108
transcript
# Reading D:/Modeltech_6.0d/tcl/vsim/pref.tcl
# // ModelSim SE 6.0d Apr 25 2005
# //
# // Copyright Mentor Graphics Corporation 2005
# // All Rights Reserved.
# //
# // THIS WO
www.eeworm.com/read/170129/9818120
vhd addsubtest.vhd
-- VHDL Test Bench Created from source file addsub.vhd -- 11:11:58 06/15/2006
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for t
www.eeworm.com/read/361567/10045619
bak dds.vhd.bak
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
package my_copponent is
component add_phase is
port(
clk:in std_logic;
fc:in std_logic
www.eeworm.com/read/361567/10045699
vhd dds.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
package my_copponent is
component add_phase is
port(
clk:in std_logic;
fc:in std_logic
www.eeworm.com/read/162983/10253989
_info
m255
13
cModel Technology
dE:\hold
Eand_gates
w985033184
DP work butter_lib DkCfIRG?QY2?20^:jcf]d3
DP ieee std_logic_unsigned hEMVMlaNCR^
www.eeworm.com/read/162699/10281506
vhd button_pio.vhd
--Copyright (C) 1991-2004 Altera Corporation
--Any megafunction design, and related net list (encrypted or decrypted),
--support information, device programming or simulation file, and any other
--
www.eeworm.com/read/420737/10778353
vhw clk_tb.vhw
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
-----------------------------------------------------
www.eeworm.com/read/271056/11010412
dec fault_cct.dec
-- Components:
-- 06.06.93 adder_1_cell
library ieee;
package fault_circuit_cmpt is
use ieee.std_logic_1164.all;
component fault_circuit
port (
a : in std_ulogic_vector(9 do