wgetinstr.vhw

用VHDL 编写的一个16位的cpu 设计方案

-- F:\CPU
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Thu Oct 20 16:48:26 2005
-- 
-- Notes:
-- 1) This testbench has been automatically generated from
--   your Test Bench Waveform
-- 2) To use this as a user modifiable testbench do the following:
--   - Save it as a file with a .vhd extension (i.e. File->Save As...)
--   - Add it to your project as a testbench source (i.e. Project->Add Source...)
-- 

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY wGetInstr IS
END wGetInstr;

ARCHITECTURE testbench_arch OF wGetInstr IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";
	COMPONENT getinstr
		PORT (
			clr : In  std_logic;
			rz : In  std_logic;
			ex : In  std_logic;
			t : In  std_logic_vector (2 DOWNTO 0);
			r7 : In  std_logic_vector (7 DOWNTO 0);
			mar : Out  std_logic_vector (15 DOWNTO 0);
			mdr : InOut  std_logic_vector (15 DOWNTO 0);
			rd : Out  std_logic;
			wr : Out  std_logic;
			opcode : InOut  std_logic_vector (3 DOWNTO 0);
			r1 : Out  std_logic_vector (2 DOWNTO 0);
			r2 : Out  std_logic_vector (2 DOWNTO 0);
			imm : Buffer  std_logic_vector (7 DOWNTO 0)
		);
	END COMPONENT;

	SIGNAL clr : std_logic;
	SIGNAL rz : std_logic;
	SIGNAL ex : std_logic;
	SIGNAL t : std_logic_vector (2 DOWNTO 0);
	SIGNAL r7 : std_logic_vector (7 DOWNTO 0);
	SIGNAL mar : std_logic_vector (15 DOWNTO 0);
	SIGNAL mdr : std_logic_vector (15 DOWNTO 0);
	SIGNAL rd : std_logic;
	SIGNAL wr : std_logic;
	SIGNAL opcode : std_logic_vector (3 DOWNTO 0);
	SIGNAL r1 : std_logic_vector (2 DOWNTO 0);
	SIGNAL r2 : std_logic_vector (2 DOWNTO 0);
	SIGNAL imm : std_logic_vector (7 DOWNTO 0);

BEGIN
	UUT : getinstr
	PORT MAP (
		clr => clr,
		rz => rz,
		ex => ex,
		t => t,
		r7 => r7,
		mar => mar,
		mdr => mdr,
		rd => rd,
		wr => wr,
		opcode => opcode,
		r1 => r1,
		r2 => r2,
		imm => imm
	);

	PROCESS
		VARIABLE TX_OUT : LINE;
		VARIABLE TX_ERROR : INTEGER := 0;

		PROCEDURE CHECK_mar(
			next_mar : std_logic_vector (15 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (mar /= next_mar) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns mar="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, mar);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_mar);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_rd(
			next_rd : std_logic;
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (rd /= next_rd) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns rd="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, rd);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_rd);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_wr(
			next_wr : std_logic;
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (wr /= next_wr) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns wr="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, wr);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_wr);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_r1(
			next_r1 : std_logic_vector (2 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (r1 /= next_r1) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns r1="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, r1);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_r1);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_r2(
			next_r2 : std_logic_vector (2 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (r2 /= next_r2) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns r2="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, r2);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_r2);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_imm(
			next_imm : std_logic_vector (7 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (imm /= next_imm) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns imm="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, imm);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_imm);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_mdr(
			next_mdr : std_logic_vector (15 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (mdr /= next_mdr) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns mdr="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, mdr);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_mdr);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_opcode(
			next_opcode : std_logic_vector (3 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (opcode /= next_opcode) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns opcode="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, opcode);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_opcode);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		BEGIN
		-- --------------------
		clr <= transport '1';
		rz <= transport '0';
		ex <= transport '0';
		t <= transport std_logic_vector'("100"); --4
		r7 <= transport std_logic_vector'("00000000"); --0
		-- --------------------
		WAIT FOR 100 ns; -- Time=100 ns
		t <= transport std_logic_vector'("010"); --2
		-- --------------------
		WAIT FOR 100 ns; -- Time=200 ns
		t <= transport std_logic_vector'("001"); --1
		-- --------------------
		WAIT FOR 100 ns; -- Time=300 ns
		ex <= transport '1';
		t <= transport std_logic_vector'("100"); --4
		-- --------------------
		WAIT FOR 100 ns; -- Time=400 ns
		t <= transport std_logic_vector'("010"); --2
		-- --------------------
		WAIT FOR 100 ns; -- Time=500 ns
		ex <= transport '0';
		t <= transport std_logic_vector'("100"); --4
		-- --------------------
		WAIT FOR 100 ns; -- Time=600 ns
		t <= transport std_logic_vector'("010"); --2
		-- --------------------
		WAIT FOR 100 ns; -- Time=700 ns
		t <= transport std_logic_vector'("001"); --1
		-- --------------------
		WAIT FOR 100 ns; -- Time=800 ns
		ex <= transport '1';
		t <= transport std_logic_vector'("100"); --4
		-- --------------------
		WAIT FOR 100 ns; -- Time=900 ns
		t <= transport std_logic_vector'("010"); --2
		-- --------------------
		WAIT FOR 100 ns; -- Time=1000 ns
		ex <= transport '0';
		t <= transport std_logic_vector'("100"); --4
		-- --------------------
		WAIT FOR 100 ns; -- Time=1100 ns
		t <= transport std_logic_vector'("010"); --2
		-- --------------------
		WAIT FOR 100 ns; -- Time=1200 ns
		t <= transport std_logic_vector'("001"); --1
		-- --------------------
		WAIT FOR 100 ns; -- Time=1300 ns
		ex <= transport '1';
		t <= transport std_logic_vector'("100"); --4
		-- --------------------
		WAIT FOR 100 ns; -- Time=1400 ns
		t <= transport std_logic_vector'("010"); --2
		-- --------------------
		WAIT FOR 100 ns; -- Time=1500 ns
		ex <= transport '0';
		-- --------------------
		WAIT FOR 200 ns; -- Time=1700 ns
		-- --------------------

		IF (TX_ERROR = 0) THEN 
			STD.TEXTIO.write(TX_OUT,string'("No errors or warnings"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Simulation successful (not a failure).  No problems detected. "
				SEVERITY FAILURE;
		ELSE
			STD.TEXTIO.write(TX_OUT, TX_ERROR);
			STD.TEXTIO.write(TX_OUT, string'(
				" errors found in simulation"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Errors found during simulation"
				SEVERITY FAILURE;
		END IF;
	END PROCESS;
END testbench_arch;

CONFIGURATION getinstr_cfg OF wGetInstr IS
	FOR testbench_arch
	END FOR;
END getinstr_cfg;