dds.vhd.bak

基于VHDL+FPGA的DDS信号发生设计

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
package my_copponent is
component add_phase is
port(
clk:in std_logic;
fc:in std_logic_vector(15 downto 0);
adderss:out std_logic_vector(15 downto 0)
); end component;
component rom is
	PORT
	(
	  clock		: IN STD_LOGIC ;
		address		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
		
		q		: OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
	);end component;
end my_copponent;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.my_copponent.all;

entity dds is 
port(
clk:in std_logic;
fctro:in std_logic_vector(15 downto 0);
addout:out std_logic_vector(15 downto 0)
);end dds;

architecture dds of dds is
signal adderss_out:std_logic_vector(15 downto 0);
signal aa:std_logic_vector(11 downto 0);
begin
u1: add_phase port map(clk,fctro,adderss_out);
aa<=adderss_out(15 downto 4);
u2: rom port map(clock=>clk,address=>aa,q=>addout);

end dds;