addsubtest.vhd

实验课的作业

-- VHDL Test Bench Created from source file addsub.vhd -- 11:11:58 06/15/2006
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;  
use IEEE.STD_LOGIC_ARITH.ALL; 


ENTITY addsub_addsubtest_vhd_tb IS
END addsub_addsubtest_vhd_tb;

ARCHITECTURE behavior OF addsub_addsubtest_vhd_tb IS 

	COMPONENT addsub
	PORT(
		X : IN std_logic_vector(3 downto 0);
		Y : IN std_logic_vector(3 downto 0);
		S : IN std_logic;
		Cin : IN std_logic;          
		F : OUT std_logic_vector(3 downto 0);
		Cout : OUT std_logic
		);
	END COMPONENT;

	SIGNAL X :  std_logic_vector(3 downto 0);
	SIGNAL Y :  std_logic_vector(3 downto 0);
	SIGNAL S :  std_logic;
	SIGNAL Cin :  std_logic;
	SIGNAL F :  std_logic_vector(3 downto 0);
	SIGNAL Cout :  std_logic;

BEGIN

	uut: addsub PORT MAP(
		X => X,
		Y => Y,
		S => S,
		Cin => Cin,
		F => F,
		Cout => Cout
	);


-- *** Test Bench - User Defined Section ***
   tb : PROCESS
   BEGIN
      X <= CONV_STD_LOGIC_VECTOR (6, 4);
	 Y <= CONV_STD_LOGIC_VECTOR (-5, 4);
	 Cin<='0';S<='0';
	 wait for 50 ns;
	 X <= CONV_STD_LOGIC_VECTOR (6, 4);
	 Y <= CONV_STD_LOGIC_VECTOR (5, 4);
	 Cin<='0';S<='0';
	 wait for 50 ns;
	 X <= CONV_STD_LOGIC_VECTOR (-6, 4);
	 Y <= CONV_STD_LOGIC_VECTOR (2, 4);
	 Cin<='0';S<='0';
	 wait for 50 ns;
	 X <= CONV_STD_LOGIC_VECTOR (1, 4);
	 Y <= CONV_STD_LOGIC_VECTOR (-5, 4);
	 Cin<='0';S<='0';
	 wait for 50 ns;
	 X <= CONV_STD_LOGIC_VECTOR (6, 4);
	 Y <= CONV_STD_LOGIC_VECTOR (-3, 4);
	 Cin<='0';S<='0';
	 wait for 50 ns;

	 wait;

   END PROCESS;
-- *** End Test Bench - User Defined Section ***

END;