代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/334523/12596036
vhd fenlu.vhd
Library ieee; --输出选择模块
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity fenlu is
Port(clk,reset,set:in std_logic;
en:in
www.eeworm.com/read/334523/12596608
vhd year1.vhd
Library ieee; --年份模块
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity year1 is
Port(clky,set,reset:in std_logic;
y1,
www.eeworm.com/read/146918/12603040
vhd my_d.vhd
-- MAX+plus II VHDL
-- Clearable my_d
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY my_d IS
PORT
(
d,sd,rd : IN STD_LOGIC;
clk : IN STD_LOGIC;
q,nq : OUT STD_L
www.eeworm.com/read/146918/12603426
vhd my_d.vhd
-- MAX+plus II VHDL
-- Clearable my_d
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY my_d IS
PORT
(
d,sd,rd : IN STD_LOGIC;
clk : IN STD_LOGIC;
q,nq : OUT STD_L
www.eeworm.com/read/146762/12614621
vhd keyboard.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity KeyBoard is
port(
clk8HZ,reset:in std_logic;
kb0 :inout std_logic;
g
www.eeworm.com/read/146761/12614982
vhd keyboard.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity KeyBoard is
port(
clk,reset:in std_logic;
kb0 :inout std_logic;
getk
www.eeworm.com/read/146662/12627155
vhd xspfpga.vhd
--------------------------------------------------------------------------------
-- Copyright (c) 2000 by Trenz Electronic.
-- Duenner Kirchweg 77, 32257 Buende, Germany, www.trenz-electronic.de
--
www.eeworm.com/read/146473/12645122
vhd uc_interface.vhd
-- File: uC_interface.vhd
--
-- Author: Jennifer Jenkins
-- Xilinx
-- Purpose: Description of an interface with a Hitachi SH7750 uC
-- bus to internal module registers
--
www.eeworm.com/read/146466/12645827
vhr vhpl1.vhr
5
0 comp_gen behaviour work
2 comp_gen behaviour work
2 comp_gen NULL work
2 std_logic_1164 NULL ieee
2 standard NULL std