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<BODY><PRE>--
-- Copyright (c) 2002 by Aldec, Inc. All rights reserved.
--
------------------------------------------------------------------------------------
-- DESCRIPTION : Component was generated by Aldec IP CORE Generator, version 3.0
-- Details:
-- C-16450 serial asynchronous transciver
-- Blocks included:
-- Interrupt Control Logic
-- Modem Control Logic
-- Baud Generator
-- CREATED : 2004-8-31, 22:53:38
------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity Registers is
port(
CS0 : in std_logic;
CS1 : in std_logic;
CS2 : in std_logic;
CSOUT : out std_logic;
DDIS : out std_logic;
A : in std_logic_vector(2 downto 0);
RESET : in std_logic;
THR_EN : out std_logic;
RHR_EN : out std_logic;
IER_EN : out std_logic;
IID_EN : out std_logic;
MCR_EN : out std_logic;
MSR_EN : out std_logic;
LSR_EN : out std_logic;
WR : in std_logic;
RD : in std_logic;
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
DIV_REG_OUT : out std_logic_vector(15 downto 0);
WORD_LEN : out std_logic_vector(1 downto 0);
RHR : in std_logic_vector(7 downto 0);
MCR : in std_logic_vector(4 downto 0);
MSR : in std_logic_vector(7 downto 0);
LSR_LSB : in std_logic_vector(4 downto 0);
LSR_MSB : in std_logic_vector(1 downto 0);
IER : in std_logic_vector(3 downto 0);
IID : in std_logic_vector(2 downto 0);
BREAK : out std_logic;
STICK_PARITY : out std_logic;
PARITY_EVEN_nODD : out std_logic;
STOP_BITS : out std_logic;
PARITY_ENABLE : out std_logic
);
end entity;
architecture Registers_ARCH of Registers is
signal LSB, MSB : STD_LOGIC_VECTOR(7 downto 0);
signal LCR : STD_LOGIC_VECTOR(7 downto 0);
signal SCRATCH : STD_LOGIC_VECTOR(7 downto 0);
signal CS : STD_LOGIC;
signal DRAB : STD_LOGIC;
signal THR_SELECT : STD_LOGIC;
signal RHR_SELECT : STD_LOGIC;
signal DIV_LSB_SELECT : STD_LOGIC;
signal DIV_MSB_SELECT : STD_LOGIC;
signal IER_SELECT : STD_LOGIC;
signal IID_SELECT : STD_LOGIC;
signal LCR_SELECT : STD_LOGIC;
signal MCR_SELECT : STD_LOGIC;
signal LSR_SELECT : STD_LOGIC;
signal MSR_SELECT : STD_LOGIC;
signal SCRATCH_SELECT : STD_LOGIC;
constant RHR_ADDRESS : STD_LOGIC_VECTOR(2 downto 0) := "000";
constant THR_ADDRESS : STD_LOGIC_VECTOR(2 downto 0) := "000";
constant DIV_LSB_ADDRESS : STD_LOGIC_VECTOR(2 downto 0) := "000";
constant DIV_MSB_ADDRESS : STD_LOGIC_VECTOR(2 downto 0) := "001";
constant IER_ADDRESS : STD_LOGIC_VECTOR(2 downto 0) := "001";
constant IID_ADDRESS : STD_LOGIC_VECTOR(2 downto 0) := "010";
constant LCR_ADDRESS : STD_LOGIC_VECTOR(2 downto 0) := "011";
constant MCR_ADDRESS : STD_LOGIC_VECTOR(2 downto 0) := "100";
constant LSR_ADDRESS : STD_LOGIC_VECTOR(2 downto 0) := "101";
constant MSR_ADDRESS : STD_LOGIC_VECTOR(2 downto 0) := "110";
constant SCRATCH_ADDRESS : STD_LOGIC_VECTOR(2 downto 0):="111";
begin
CS <= CS0 and CS1 and not CS2;
DDIS <= not RD and CS;
CSOUT <= CS;
THR_SELECT <= '1' when (A = THR_ADDRESS and DRAB = '0' and CS = '1') else '0';
RHR_SELECT <= '1' when (A = RHR_ADDRESS and DRAB = '0' and CS = '1') else '0';
DIV_LSB_SELECT <= '1' when (A = DIV_LSB_ADDRESS and DRAB = '1' and CS = '1') else '0';
DIV_MSB_SELECT <= '1' when (A = DIV_MSB_ADDRESS and DRAB = '1' and CS = '1') else '0';
IER_SELECT <= '1' when (A = IER_ADDRESS and DRAB = '0' and CS = '1') else '0';
IID_SELECT <= '1' when (A = IID_ADDRESS and CS = '1') else '0';
LCR_SELECT <= '1' when (A = LCR_ADDRESS and CS = '1') else '0';
MCR_SELECT <= '1' when (A = MCR_ADDRESS and CS = '1') else '0';
LSR_SELECT <= '1' when (A = LSR_ADDRESS and CS = '1') else '0';
MSR_SELECT <= '1' when (A = MSR_ADDRESS and CS = '1') else '0';
SCRATCH_SELECT <= '1' when (A = SCRATCH_ADDRESS and CS = '1') else '0';
THR_EN <= THR_SELECT;
RHR_EN <= RHR_SELECT;
IER_EN <= IER_SELECT;
IID_EN <= IID_SELECT;
MCR_EN <= MCR_SELECT;
LSR_EN <= LSR_SELECT;
MSR_EN <= MSR_SELECT;
process(WR, RESET)
begin
if (RESET = '0') then
LSB <= "00000001";
elsif (rising_edge(WR)) then
if (DIV_LSB_SELECT = '1') then
LSB <= DATA_IN;
end if;
end if;
end process;
process(WR, RESET)
begin
if (RESET = '0') then
MSB <= "00000000";
elsif (rising_edge(WR)) then
if (DIV_MSB_SELECT = '1') then
MSB <= DATA_IN;
end if;
end if;
end process;
DIV_REG_OUT <= MSB & LSB;
process(WR, RESET)
begin
if (RESET = '0') then
SCRATCH <= "00000000";
elsif (rising_edge(WR)) then
if (SCRATCH_SELECT = '1') then
SCRATCH <= DATA_IN;
end if;
end if;
end process;
process(WR, RESET)
begin
if (RESET = '0') then
LCR <= "00011000";
elsif (rising_edge(WR)) then
if (LCR_SELECT = '1') then
LCR <= DATA_IN;
end if;
end if;
end process;
WORD_LEN <= LCR(1 downto 0);
DRAB <= LCR(7);
BREAK <= LCR(6);
STOP_BITS <= LCR(2);
PARITY_ENABLE <= LCR(3);
PARITY_EVEN_nODD <= LCR(4);
STICK_PARITY <= LCR(5);
process(A, LCR, SCRATCH, RHR, LSR_LSB, DRAB, LSB, MSB, LSR_MSB, IER, IID, MCR, MSR)
begin
case (A) is
when RHR_ADDRESS =>
if (DRAB = '0') then
DATA_OUT <= RHR;
else
DATA_OUT <= LSB;
end if;
when IER_ADDRESS =>
if (DRAB = '0') then
DATA_OUT <= ("0000" & IER);
else
DATA_OUT <= MSB;
end if;
when IID_ADDRESS => DATA_OUT <= ("00000" & IID);
when LCR_ADDRESS => DATA_OUT <= LCR;
when MCR_ADDRESS => DATA_OUT <= ("000" & MCR);
when LSR_ADDRESS => DATA_OUT <= ('0' & LSR_MSB & LSR_LSB);
when MSR_ADDRESS => DATA_OUT <= MSR;
when SCRATCH_ADDRESS => DATA_OUT <= SCRATCH;
when others => DATA_OUT <= "00000000";
end case;
end process;
end architecture;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ReceiverCore is
port(
CLK : in std_logic;
RESET : in std_logic;
CE : in std_logic;
LOOPBACK : in std_logic;
EXTERNAL_SERIAL_IN : in std_logic;
INTERNAL_SERIAL_IN : in std_logic;
RHR_OUT : out std_logic_vector(7 downto 0);
LSR_OUT : out std_logic_vector(4 downto 0);
BITS_COUNT : in std_logic_vector(1 downto 0);
PARITY_ENABLE : in std_logic;
PARITY_EVEN_nODD : in std_logic;
STICK_PARITY : in std_logic;
RD : in std_logic;
LINE_STATUS_INTERRUPT : out std_logic;
RECEIVER_INTERRUPT : out std_logic;
RHR_EN : in std_logic;
LSR_EN : in std_logic
);
end entity;
architecture ReceiverCore_ARCH of ReceiverCore is
constant IDLE_STATE : STD_LOGIC_VECTOR(3 downto 0) := "0000";
constant START_STATE : STD_LOGIC_VECTOR(3 downto 0) := "0001";
constant BIT0_STATE : STD_LOGIC_VECTOR(3 downto 0) := "1001";
constant BIT1_STATE : STD_LOGIC_VECTOR(3 downto 0) := "1011";
constant BIT2_STATE : STD_LOGIC_VECTOR(3 downto 0) := "1010";
constant BIT3_STATE : STD_LOGIC_VECTOR(3 downto 0) := "1000";
constant BIT4_STATE : STD_LOGIC_VECTOR(3 downto 0) := "1100";
constant BIT5_STATE : STD_LOGIC_VECTOR(3 downto 0) := "1101";
constant BIT6_STATE : STD_LOGIC_VECTOR(3 downto 0) := "1111";
constant BIT7_STATE : STD_LOGIC_VECTOR(3 downto 0) := "1110";
constant PARITY_STATE : STD_LOGIC_VECTOR(3 downto 0) := "0101";
constant STOP_STATE : STD_LOGIC_VECTOR(3 downto 0) := "0111";
constant BREAK_STATE : STD_LOGIC_VECTOR(3 downto 0) := "0011";
signal RECEIVING_DATA_BIT : STD_LOGIC;
signal RECEIVING_PARITY_BIT : STD_LOGIC;
signal RECEIVING_STOP_BIT : STD_LOGIC;
signal RECEIVER_IDLE : STD_LOGIC;
signal RECEIVER_IDLE_BREAK : STD_LOGIC;
signal RECEIVER_STATE : STD_LOGIC_VECTOR(3 downto 0);
signal SHIFT_REGISTER : STD_LOGIC_VECTOR(7 downto 0);
signal SHIFT_REGISTER_INPUT : STD_LOGIC_VECTOR(7 downto 0);
signal RECEIVER_HOLDING_REGISTER : STD_LOGIC_VECTOR(7 downto 0);
signal RHR_FULL : STD_LOGIC;
signal RHR_FULL_RESET : STD_LOGIC;
signal RHR_WRITE_ENABLE : STD_LOGIC;
signal CALCULATED_PARITY : STD_LOGIC;
signal PARITY_REGISTER : STD_LOGIC;
signal START_CONFIRMED : STD_LOGIC;
signal CLOCK_DIVIDER : STD_LOGIC_VECTOR(3 downto 0);
signal RELOAD_COUNTER : STD_LOGIC;
signal NEXT_STATE : STD_LOGIC;
signal BREAK_DETECTED : STD_LOGIC;
signal RESET_BREAK_DETECTED : STD_LOGIC;
signal BREAK_DETECTOR : STD_LOGIC;
signal CATCH_ENABLE : STD_LOGIC;
signal RESET_FRAME_ERROR : STD_LOGIC;
signal FRAME_ERROR : STD_LOGIC;
signal RESET_OVERRUN_ERROR : STD_LOGIC;
signal OVERRUN_ERROR : STD_LOGIC;
signal RESET_PARITY_ERROR : STD_LOGIC;
signal PARITY_ERROR : STD_LOGIC;
signal PARITY_OK : STD_LOGIC;
signal STOP_BIT : STD_LOGIC;
signal SERIAL_IN : STD_LOGIC;
begin
RECEIVING_DATA_BIT <= RECEIVER_STATE(3);
RECEIVING_PARITY_BIT <= '1' when RECEIVER_STATE(3 downto 1) = "010" else '0';
RECEIVING_STOP_BIT <= '1' when RECEIVER_STATE(3 downto 1) = "011" else '0';
RECEIVER_IDLE <= not (RECEIVER_STATE(3) or RECEIVER_STATE(0));
RECEIVER_IDLE_BREAK <= '1' when RECEIVER_STATE = "0011" or RECEIVER_STATE = "0000" else '0';
process(CLK, RESET)
begin
if (RESET = '0') then
SERIAL_IN <= '1';
elsif (rising_edge(CLK)) then
if (CE = '1') then
if (LOOPBACK = '1') then
SERIAL_IN <= INTERNAL_SERIAL_IN;
else
SERIAL_IN <= EXTERNAL_SERIAL_IN;
end if;
end if;
end if;
end process;
process(CLK, RESET)
begin
if (RESET = '0') then
STOP_BIT <= '1';
elsif (rising_edge(CLK)) then
if ((CATCH_ENABLE = '1') and (RECEIVING_STOP_BIT = '1')) then
STOP_BIT <= SERIAL_IN;
end if;
end if;
end process;
process(CLK, RESET)
begin
if (RESET = '0') then
PARITY_REGISTER <= '0';
elsif (rising_edge(CLK)) then
if (CATCH_ENABLE = '1') then
if (PARITY_ENABLE = '0') then
PARITY_REGISTER <= '0';
elsif (RECEIVING_PARITY_BIT = '1') then
PARITY_REGISTER <= SERIAL_IN;
end if;
end if;
end if;
end process;
process(RD, RESET, BREAK_DETECTED)
begin
if ((RESET = '0') or (BREAK_DETECTED = '0')) then
RESET_BREAK_DETECTED <= '0';
elsif (rising_edge(RD)) then
RESET_BREAK_DETECTED <= LSR_EN;
end if;
end process;
process(CLK, RESET, RESET_BREAK_DETECTED)
begin
if ((RESET = '0') or (RESET_BREAK_DETECTED = '1')) then
BREAK_DETECTED <= '0';
elsif (rising_edge(CLK)) then
if ((NEXT_STATE = '1') and (RECEIVING_STOP_BIT = '1')) then
BREAK_DETECTED <= BREAK_DETECTED or not (BREAK_DETECTOR or STOP_BIT or PARITY_REGISTER);
end if;
end if;
end process;
process(RESET, CLK)
begin
if (RESET = '0') then
BREAK_DETECTOR <= '0';
elsif (rising_edge(CLK)) then
if (CE = '1') then
if (RECEIVING_DATA_BIT = '1') then
BREAK_DETECTOR <= BREAK_DETECTOR or SERIAL_IN;
elsif (RECEIVER_IDLE_BREAK = '1') then
BREAK_DETECTOR <= '0';
end if;
end if;
end if;
end process;
process(CLK, RESET)
begin
if (RESET = '0') then
START_CONFIRMED <= '0';
elsif (rising_edge(CLK)) then
if (CATCH_ENABLE = '1') then
START_CONFIRMED <= not SERIAL_IN;
end if;
end if;
end process;
SHIFT_REGISTER_INPUT(7) <= BITS_COUNT(0) and BITS_COUNT(1) and SERIAL_IN;
SHIFT_REGISTER_INPUT(6) <= BITS_COUNT(1) and ((BITS_COUNT(0) and SHIFT_REGISTER(7)) or (not BITS_COUNT(0) and SERIAL_IN));
SHIFT_REGISTER_INPUT(5) <= (BITS_COUNT(1) and SHIFT_REGISTER(6)) or (not BITS_COUNT(1) and BITS_COUNT(0) and SERIAL_IN);
SHIFT_REGISTER_INPUT(4) <= (not BITS_COUNT(0) and not BITS_COUNT(1) and SERIAL_IN) or ((BITS_COUNT(0) or BITS_COUNT(1)) and SHIFT_REGISTER(5));
SHIFT_REGISTER_INPUT(3 downto 0) <= SHIFT_REGISTER(4 downto 1);
process(CLK, RESET)
begin
if (RESET = '0') then
SHIFT_REGISTER <= "00000000";
elsif (rising_edge(CLK)) then
if ((CATCH_ENABLE = '1') and (RECEIVING_DATA_BIT = '1')) then
SHIFT_REGISTER <= SHIFT_REGISTER_INPUT;
end if;
end if;
end process;
process(RESET, FRAME_ERROR, RD)
begin
if ((RESET = '0') or (FRAME_ERROR = '0')) then
RESET_FRAME_ERROR <= '0';
elsif (rising_edge(RD)) then
RESET_FRAME_ERROR <= LSR_EN;
end if;
end process;
process(RESET, RESET_FRAME_ERROR, CLK)
begin
if ((RESET = '0') or (RESET_FRAME_ERROR = '1')) then
FRAME_ERROR <= '0';
elsif (rising_edge(CLK)) then
if (CE = '1') then
if (RHR_WRITE_ENABLE = '1') then
FRAME_ERROR <= not STOP_BIT;
end if;
end if;
end if;
end process;
process(RESET, OVERRUN_ERROR, RD)
begin
if ((RESET = '0') or (OVERRUN_ERROR = '0')) then
RESET_OVERRUN_ERROR <= '0';
elsif (rising_edge(RD)) then
RESET_OVERRUN_ERROR <= LSR_EN;
end if;
end process;
process(CLK, RESET, RESET_OVERRUN_ERROR)
begin
if ((RESET = '0') or (RESET_OVERRUN_ERROR = '1')) then
OVERRUN_ERROR <= '0';
elsif (rising_edge(CLK)) then
if (CE = '1') then
if (RHR_WRITE_ENABLE = '1') then
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