year1.vhd

能自动记时

Library ieee;             --年份模块
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity year1 is
 Port(clky,set,reset:in std_logic;
               y1,y0:in std_logic_vector(3 downto 0);         --输入预置年份
         year1,year0:buffer std_logic_vector(3 downto 0));    --输出年份显示
End  year1;                 
Architecture one of year1 is
Begin
Process(clky,reset,set,y1,y0)
   variable  cq1,cq0: STD_LOGIC_vector( 3 downto 0);
Begin
   if reset='1' then cq1:="0000"; cq0:="0000";  
      Elsif clky'event and clky='1' then  cq0:=cq0+1;   
        if  cq0="1010" then  cq0:="0000";cq1:=cq1+1;    --年份低位满10，低位返回00重复计数，高位加1
        if  cq1="1010" then cq1:="0000";                --年份高位满10，返回重复计数
        end if;    
        end if;
   end if;
   year1<=cq1;year0<=cq0;
End process;
End one;