my_d.vhd

大学vhdl语言实验大全,基于max-plus2平台,内有8-3译码器,8位加法器,数字钟

-- MAX+plus II VHDL 
-- Clearable my_d

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY my_d IS

	PORT
	(
		d,sd,rd		    : IN	STD_LOGIC;
		clk  	    : IN	STD_LOGIC;
		q,nq		: OUT 	STD_LOGIC
	);
end my_d;

ARCHITECTURE behave OF my_d IS
signal tt,kk,ll:std_logic;
BEGIN
   tt<=d;
P1:Process(rd,sd,clk)
   begin 
  if(clk='1' and clk'event) then
     if (sd='1' and rd='1')then 
        kk<=tt;
        ll<=not tt;
    end if;
  end if;
    q<=kk;
    nq<=ll;
   if(sd='1' and rd='0')then q<='0';nq<='1'; 
    end if;
  if(sd='0' and rd='1')then  q<='1';nq<='0';
    end if;
end Process;

END behave;