代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/218836/14904701
vhd program-h.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity newhour is
port (carrym,reset:in std_logic;
Hhour,Lhour: out std_logic_vector(3 downto 0));
end newho
www.eeworm.com/read/216963/14983995
vhd xil_rgb2ycrcb_sg_wrap.vhd
--*******************************************************************
-- Copyright(C) 2005 by Xilinx, Inc. All rights reserved.
-- This text/file contains proprietary, confidential
-- information of X
www.eeworm.com/read/216955/14984351
vhd counter.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY COUNTER IS
PORT( CLK:IN STD_LOGIC;
EN: IN STD_LOGIC;
S: IN STD_LOGIC;
LOAD: IN STD_LOGI
www.eeworm.com/read/215048/15076303
vhd modelctrl.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity modelctrl is
port(
model: in std_logic;
stanum: out std_logic_vector(6 downto 0);
ctrl: out std_logi
www.eeworm.com/read/214183/15111448
vhd conve.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity convert is
Port (
enable : in std_logic;
clk : in std_lo
www.eeworm.com/read/213714/15127520
txt taxijifeiqi.txt
--实验十四 出租车计费器
--里程计算模块
-- LCJS.VHD
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity LCJS is
GENERIC(--0:INTEGER:=160 ; --
www.eeworm.com/read/213596/15129700
vhd cornaa.vhd
library ieee;
use ieee.std_logic_1164.all;
entity cornaa is -----LOAD 为设置密码的开关
port(clk,k1,k0,clr,load:in std_logic; -----K1，K0 分别是代表1和0的按键开关
lt:inout std_logi
www.eeworm.com/read/213523/15130876
vhd t2t.vhd
-- MAX+plus II VHDL Template
-- Clearable flipflop with enable
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY T2T IS
PORT
(
data : in std_logic_vector(7 downto 0);
dataout, q
www.eeworm.com/read/213523/15130879
vhd r2r.vhd
-- MAX+plus II VHDL Template
-- Clearable flipflop with enable
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY R2R IS
PORT
(
data : in std_logic_vector(7 downto 0);
dataout, q
www.eeworm.com/read/211745/15174418
vhd txmit.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity txmit is
port(
tx:out std_logic;
--data:in std_logic_vector(7 downto 0);
mclk_16,write:in std_logic