t2t.vhd

用VHDL实现的通信滑码处理

-- MAX+plus II VHDL Template
-- Clearable flipflop with enable

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY T2T IS

	PORT
	(
		data 			: in	std_logic_vector(7 downto 0);
		dataout, q		: out	std_logic_vector(7 downto 0 );
		C2, C3, C8		: IN	STD_LOGIC;
		COUT, RD, WR	: OUT	STD_LOGIC;
		slot			: out	std_logic
	);
	
END T2T;

ARCHITECTURE a OF T2T IS
COMPONENT LPM_FIFO
	GENERIC (LPM_WIDTH: POSITIVE;
		LPM_WIDTHU: POSITIVE := 1;
		LPM_TYPE: STRING := "LPM_FIFO";
		LPM_NUMWORDS: POSITIVE;
		LPM_SHOWAHEAD: STRING := "OFF";
		LPM_HINT: STRING := "UNUSED");
	PORT (data: IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);
		clock, rdreq, wrreq: IN STD_LOGIC;
		aclr, sclr: IN STD_LOGIC := '0';
		full, empty: OUT STD_LOGIC;
		usedw: OUT STD_LOGIC_VECTOR(LPM_WIDTHU-1 DOWNTO 0);
		q: OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0)

	);
END COMPONENT;

	SIGNAL	c2i, c3i, c2flag, c3flag, read, write : STD_LOGIC;
	signal  clock, full, empty, aclr, sclr : std_logic;
	signal usedw : std_logic_vector( 6 downto 0);
	signal qi, datai : std_logic_vector( 7 downto 0);
	signal sloti, startSend : std_logic;
	signal dataout0 : std_logic_vector( 7 downto 0);
	
BEGIN
U1: LPM_FIFO
	GENERIC map ( 8, 7, "LPM_FIFO", 128, "OFF", "UNUSED")
	PORT map (data, clock, read, write, aclr, sclr, full, empty, usedw, qi );

	aclr <= '0';
	sclr <= '0';
	
	RD <= read;
	WR <= write;
	cout <= clock;
	q <= qi;
	slot <= sloti;

	process( c8 ) begin
		if( c8='1' ) then
			c2i<=c2;
			c3i<=c3;
			if( c2i='0' and c2='1' ) then
				c2flag <='1';
			elsif( write='1' or (c2i='1' and c2='0') ) then
				c2flag <='0';
			end if;

			if( c3i='0' and c3='1' ) then
				c3flag <='1';
			elsif( read='1' or (c3i='1' and c3='0') ) then
				c3flag <='0';
			end if;
		end if;
	end process;

	
	process( c8 )
		variable sts : integer range 0 to 3;
		variable cnt : integer range 0 to 15;
	BEGIN
		if( c8='1' ) then
			CASE sts IS
				WHEN 0 => 
	    			if( c2flag='1' ) then
						sts:=1;
						write <= '1'; 
					elsif( c3flag='1' ) then
						if( startSend='0' ) then
							if( usedw(6 downto 4) /= "000" ) then
								startSend <= '1';
								cnt := 0;
								datai <= "00000000";
							else
								datai <= "11111111";
							end if;
							sts := 2;
							sloti <= '1';
						else
							if( cnt = 15 ) then startSend <= '0'; end if;
							cnt := cnt + 1;
							sts := 1;
						end if;
						read <= '1';
					
					end if;
				WHEN 1 =>
					sts := 2;
					clock <= '1';
				when 2 =>
					sts := 3;
					clock <= '0';
				WHEN OTHERS =>
					sts := 0;	
					write <= '0';
					read <= '0';
					if( write='0' ) then
						if( sloti='0' ) then
							dataout0<=qi;
						else
							dataout0<=datai;
						end if;
					end if; 
					sloti <= '0';
			END CASE;
		end if;
	end process;

	process( C3 ) begin if( C3='1') then dataout<=dataout0; end if; end process;

	
END a;