program-h.vhd

来自「last time when i came here to find some 」· VHDL 代码 · 共 31 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity newhour is
  port (carrym,reset:in std_logic;
        Hhour,Lhour: out std_logic_vector(3 downto 0));
end newhour;
architecture t1 of newhour is
signal hourt1,hourt2: std_logic_vector(3 downto 0);
begin
process(reset,carrym)
    begin
    if reset='1' then
       hourt1<="0000";
       hourt2<="0000";
    elsif (carrym'event and carrym='1') then
        if hourt1="1001" or (hourt1="0011" and hourt2="0010") then
           hourt1<="0000";
            if hourt2="0010"  then
               hourt2<="0000";
            else
              hourt2<=hourt2+1;
            end if;
        else 	hourt1<=hourt1+1;
        end if;
        end if;
    end process;
        Lhour<=hourt1;
        Hhour<=hourt2;
end t1;