counter.vhd

我们学校做VHDL实验的源码

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY COUNTER IS
 PORT( CLK:IN STD_LOGIC;
       EN: IN STD_LOGIC;
        S: IN STD_LOGIC;
       LOAD: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
          C: OUT STD_LOGIC;
       JISHU: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
     );
END ENTITY;
 ARCHITECTURE BHV OF COUNTER IS
   SIGNAL TEMP:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
   PROCESS(EN,CLK,S,LOAD)
      BEGIN
        IF CLK'EVENT AND CLK='1' THEN
          IF(EN='1')   
          THEN IF(S='1') THEN TEMP<=LOAD;
               ELSIF(TEMP<9) THEN TEMP<=TEMP+1; C<='0';
                   ELSE TEMP<="0000";
                       C<='1';
               END IF;
           END IF;
         END IF;
          
        
        
    END PROCESS;
    JISHU<=TEMP;
END BHV;