代码搜索：simulate

找到约 2,241 项符合「simulate」的源代码

代码结果 2,241
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/177213/9464785

gfl clk_div3.gfl

# XST (Creating Lso File) : clk_div3.lso # xst flow : RunXST clk_div3.syr clk_div3.prj clk_div3.sprj clk_div3.ana clk_div3.stx clk_div3.cmd_log # XST (Creating Lso File) : clk_div3.lso #
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www.eeworm.com/read/170129/9818113

gfl lab2.gfl

# ProjNav -> New -> Test Bench __projnav/createTB.err # ModelSim : Simulate Behavioral VHDL Model addsub_addsubtest_vhd_tb.fdo # ModelSim : Simulate Behavioral VHDL Model vsim.wlf # ModelSim : S
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www.eeworm.com/read/162348/10312366

gfl ex.gfl

# ModelSim : Simulate Behavioral VHDL Model receive_rec_tb_vhd_tb.fdo # ModelSim : Simulate Behavioral VHDL Model vsim.wlf # ModelSim : Simulate Behavioral VHDL Model vsim.wlf # ModelSim : Simul
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www.eeworm.com/read/331394/7072238

ini debuginsimulator.ini

// Simulate AT24C02 256*8bit EEPROM map 0x33FFFF00, 0x33FFFFA0 read write exec
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www.eeworm.com/read/462649/7198668

gfl p1_crc_gen.gfl

# XST (Creating Lso File) : tipod.lso # xst flow : RunXST tipod_summary.html # xst flow : RunXST tipod.syr tipod.prj tipod.sprj tipod.ana tipod.stx tipod.cmd_log tipod.ngc tipod.ngr # XS
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www.eeworm.com/read/458723/7290686

h pda.h

/*======================================================================== * * 版权所有 (C) 2000-2001 []公司. All Rights Reserved. * * 文件: pda.h * 内容: PSDE系统之All in one头文件。 * 作者: 吴柏建
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www.eeworm.com/read/458154/7303314

h pda.h

/*======================================================================== * * 版权所有 (C) 2000-2001 []公司. All Rights Reserved. * * 文件: pda.h * 内容: PSDE_DEMO_PDA系统之All in one头文件。 *
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www.eeworm.com/read/151067/5687071

ref reedsolomon.ref

Number of Reed-Solomon code-words to simulate: 1000 BSC Error probability : 0.01 RS m: 3 RS t: 2 Simulating an Reed-Solomon code with the following parameters: n = 7 k = 3 q = 8 The bit error probabil
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www.eeworm.com/read/140582/5786634

sh eastrun.sh

: This should fail, but only because .1 of westnests has no TXT. : We use --up so that the negotiation is logged. : Failure should come before negotiation is actually started. : No shunt eroute will b
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www.eeworm.com/read/477386/6733980

txt 时序仿真.txt

查看Quartus 6.0的帮助文件，试验了一下可以进行时序仿真，以前看到过一些相关文章，但都没有成功，关键的一个问题就是没有编译库文件，总结步骤如下(本人用Verilog，括号中给出了用VHDL时的相关提示： ［注］Quartus版本为 6.0，ModelSim为 6.2a，其它版本可能稍有不同 方法一、根据Quartus帮助文件改写 1、File > Change Directo ...
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