📄 p1_crc_gen.gfl

📁 This Circuit generates the syndrome for the CRC. This is quite useful for transmision purposes and e
💻 GFL
字号:
# XST (Creating Lso File) : 
tipod.lso
# xst flow : RunXST
tipod_summary.html
# xst flow : RunXST
tipod.syr
tipod.prj
tipod.sprj
tipod.ana
tipod.stx
tipod.cmd_log
tipod.ngc
tipod.ngr
# XST (Creating Lso File) : 
crc.lso
# xst flow : RunXST
crc_summary.html
# xst flow : RunXST
crc.syr
crc.prj
crc.sprj
crc.ana
crc.stx
crc.cmd_log
# XST (Creating Lso File) : 
crc.lso
# xst flow : RunXST
crc_summary.html
# xst flow : RunXST
crc.syr
crc.prj
crc.sprj
crc.ana
crc.stx
crc.cmd_log
tipod.ngc
crc.ngc
tipod.ngr
crc.ngr
# ProjNav -> New -> Test Bench
__projnav/createTB.err
# xst flow : RunXST
crc_summary.html
# Implmentation : Translate
__projnav/ednTOngd_tcl.rsp
"e:\practica uno/_ngo"
tipod.ngd
tipod_ngdbuild.nav
tipod.bld
.untf
tipod.cmd_log
# Implementation : Map
tipod_summary.html
# Implementation : Map
tipod_map.ncd
tipod.ngm
tipod.pcf
tipod.nc1
tipod.mrp
tipod_map.mrp
tipod.mdf
tipod.cmd_log
MAP_NO_GUIDE_FILE_CPF "tipod"
tipod_map.ngm
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
tipod.twr
tipod.twx
tipod.tsi
tipod.cmd_log
# Implementation : Place & Route
tipod_summary.html
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
tipod.ncd
tipod.par
tipod.pad
tipod_pad.txt
tipod_pad.csv
tipod.pad_txt
tipod.dly
reportgen.log
tipod.xpi
tipod.grf
tipod.itr
tipod_last_par.ncd
tipod.placed_ncd_tracker
tipod.routed_ncd_tracker
tipod.cmd_log
PAR_NO_GUIDE_FILE_CPF "tipod"
# ModelSim : Simulate Behavioral VHDL Model
prueba_vhd.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
prueba_vhd.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# XST (Creating Lso File) : 
crc.lso
# xst flow : RunXST
crc_summary.html
# xst flow : RunXST
crc.syr
crc.prj
crc.sprj
crc.ana
crc.stx
crc.cmd_log
tipod.ngc
crc.ngc
tipod.ngr
crc.ngr
# XST (Creating Lso File) : 
crc.lso
# xst flow : RunXST
crc_summary.html
# xst flow : RunXST
crc.syr
crc.prj
crc.sprj
crc.ana
crc.stx
crc.cmd_log
tipod.ngc
crc.ngc
tipod.ngr
crc.ngr
# XST (Creating Lso File) : 
crc.lso
# xst flow : RunXST
crc_summary.html
# xst flow : RunXST
crc.syr
crc.prj
crc.sprj
crc.ana
crc.stx
crc.cmd_log
tipod.ngc
crc.ngc
tipod.ngr
crc.ngr
# XST (Creating Lso File) : 
crc.lso
# xst flow : RunXST
crc_summary.html
# xst flow : RunXST
crc.syr
crc.prj
crc.sprj
crc.ana
crc.stx
crc.cmd_log
tipod.ngc
crc.ngc
tipod.ngr
crc.ngr
# Implmentation : Translate
__projnav/ednTOngd_tcl.rsp
"e:\practica uno/_ngo"
crc.ngd
crc_ngdbuild.nav
crc.bld
.untf
crc.cmd_log
# Implementation : Map
crc_summary.html
# Implementation : Map
crc_map.ncd
crc.ngm
crc.pcf
crc.nc1
crc.mrp
crc_map.mrp
crc.mdf
crc.cmd_log
MAP_NO_GUIDE_FILE_CPF "crc"
crc_map.ngm
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
crc.twr
crc.twx
crc.tsi
crc.cmd_log
# Implementation : Place & Route
crc_summary.html
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
crc.ncd
crc.par
crc.pad
crc_pad.txt
crc_pad.csv
crc.pad_txt
crc.dly
reportgen.log
crc.xpi
crc.grf
crc.itr
crc_last_par.ncd
crc.placed_ncd_tracker
crc.routed_ncd_tracker
crc.cmd_log
PAR_NO_GUIDE_FILE_CPF "crc"
# ModelSim : Simulate Behavioral VHDL Model
prueba_vhd.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
prueba_vhd.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
prueba_vhd.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
prueba_vhd.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
prueba_vhd.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
prueba_vhd.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
prueba_vhd.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
prueba_vhd.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# XST (Creating Lso File) : 
crc.lso
# xst flow : RunXST
crc_summary.html
# xst flow : RunXST
crc.syr
crc.prj
crc.sprj
crc.ana
crc.stx
crc.cmd_log
tipod.ngc
crc.ngc
tipod.ngr
crc.ngr
# Implmentation : Translate
__projnav/ednTOngd_tcl.rsp
"e:\practica uno/_ngo"
crc.ngd
crc_ngdbuild.nav
crc.bld
.untf
crc.cmd_log
# Implementation : Map
crc_summary.html
# Implementation : Map
crc_map.ncd
crc.ngm
crc.pcf
crc.nc1
crc.mrp
crc_map.mrp
crc.mdf
crc.cmd_log
MAP_NO_GUIDE_FILE_CPF "crc"
crc_map.ngm
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
crc.twr
crc.twx
crc.tsi
crc.cmd_log
# Implementation : Place & Route
crc_summary.html
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
crc.ncd
crc.par
crc.pad
crc_pad.txt
crc_pad.csv
crc.pad_txt
crc.dly
reportgen.log
crc.xpi
crc.grf
crc.itr
crc_last_par.ncd
crc.placed_ncd_tracker
crc.routed_ncd_tracker
crc.cmd_log
PAR_NO_GUIDE_FILE_CPF "crc"
# ModelSim : Simulate Behavioral VHDL Model
prueba_vhd.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
prueba_vhd.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
prueba_vhd.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
prueba_vhd.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
prueba_vhd.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
prueba_vhd.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
prueba_vhd.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
prueba_vhd.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# xst flow : RunXST
crc_summary.html
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# xst flow : RunXST
crc_summary.html
# xst flow : RunXST
crc_summary.html
# xst flow : RunXST
crc_summary.html
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# xst flow : RunXST
crc_summary.html
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# xst flow : RunXST
crc_summary.html
# xst flow : RunXST
crc_summary.html
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# xst flow : RunXST
crc_summary.html
# ModelSim : Simulate Behavioral VHDL Model
prueba_vhd.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# xst flow : RunXST
crc_summary.html
# xst flow : RunXST
crc_summary.html
# ModelSim : Simulate Behavioral VHDL Model
prueba_vhd.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# xst flow : RunXST
crc_summary.html
# xst flow : RunXST
crc_summary.html
# XST (Creating Lso File) : 
crc.lso
# xst flow : RunXST
crc_summary.html
# xst flow : RunXST
crc.syr
crc.prj
crc.sprj
crc.ana
crc.stx
crc.cmd_log
tipod.ngc
crc.ngc
tipod.ngr
crc.ngr
# Implmentation : Translate
__projnav/ednTOngd_tcl.rsp
"c:\documents and settings\administrador\mis documentos\teleco files\4 teleco\1er cuatrimestre\arquitectura de computadores [9][ac]\practicas\practica 1 generador crc/_ngo"
crc.ngd
crc_ngdbuild.nav
crc.bld
.untf
crc.cmd_log
# Implementation : Map
crc_summary.html
# Implementation : Map
crc_map.ncd
crc.ngm
crc.pcf
crc.nc1
crc.mrp
crc_map.mrp
crc.mdf
crc.cmd_log
MAP_NO_GUIDE_FILE_CPF "crc"
crc_map.ngm
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
crc.twr
crc.twx
crc.tsi
crc.cmd_log
# Implementation : Place & Route
crc_summary.html
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
crc.ncd
crc.par
crc.pad
crc_pad.txt
crc_pad.csv
crc.pad_txt
crc.dly
reportgen.log
crc.xpi
crc.grf
crc.itr
crc_last_par.ncd
crc.placed_ncd_tracker
crc.routed_ncd_tracker
crc.cmd_log
PAR_NO_GUIDE_FILE_CPF "crc"
# Implementation : Generate Post-Place & Route Simulation Model
crc_timesim.vhd
crc_timesim.nlf
crc.vhdsim_par
crc.par_nlf
crc.cmd_log
crc_timesim.vhd
crc_timesim.sdf
crc_timesim.sdf
# ModelSim : Simulate Post-Place & Route VHDL Model
prueba_vhd.tdo
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# Compile HDL Simulation Libraries
compxlib.log
P1_CRC_gen.cxl
P1_CRC_gen.compxlib_log
# Compile HDL Simulation Libraries
compxlib.log
P1_CRC_gen.cxl
P1_CRC_gen.compxlib_log
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# Generate Power Data
crc.pwr
crc_xpwr.xml
# Power Report
crc.pwr
crc_xpwr.xml
# Implementation : Guide Results Report
crc_summary.html
# Implmentation : Guide Results Report
__projnav/nc1TOncd_tcl.rsp
crc.ncd
crc.par
crc.pad
crc_pad.txt
crc_pad.csv
crc.pad_txt
crc.dly
reportgen.log
crc.xpi
crc.grf
crc.itr
crc_last_par.ncd
crc.placed_ncd_tracker
crc.routed_ncd_tracker
crc.cmd_log
PAR_NO_GUIDE_FILE_CPF "crc"
# Asynchronous Delay Report
crc.dly
reportgen.log
# Implementation : Guide Results Report
crc_summary.html
# Implmentation : Guide Results Report
__projnav/nc1TOncd_tcl.rsp
crc.ncd
crc.par
crc.pad
crc_pad.txt
crc_pad.csv
crc.pad_txt
crc.dly
reportgen.log
crc.xpi
crc.grf
crc.itr
crc_last_par.ncd
crc.placed_ncd_tracker
crc.routed_ncd_tracker
crc.cmd_log
PAR_NO_GUIDE_FILE_CPF "crc"
# Generate Programming File
__projnav/crc_ncdTOut_tcl.rsp
__projnav/bitgen.rsp
bitgen.ut
crc.ut
# Generate Programming File
crc.bgn
crc.rbt
crc.ll
crc.msk
crc.drc
crc.nky
crc.bit
crc.bin
crc.isc
crc.cmd_log
# Implementation : Post-Synthesis Simulation Model Report
crc_synthesis.vhd
crc_synthesis.nlf
crc.vhdsim_synth
crc.synth_nlf
crc.cmd_log
crc_synthesis.vhd
# Implementation : Generate IBIS Model (FPGA Flow)
crc.ibs
crc.cmd_log
# Implementation : Multi Pass Place & Route
mppr_result.par
c:\documents and settings\administrador\mis documentos\teleco files\4 teleco\1er cuatrimestre\arquitectura de computadores [9][ac]\practicas\practica 1 generador crc/mppr_result.dir
crc.par
crc.ncd
crc.pad
crc.dly
crc.xpi
crc.mppr
crc.cmd_log
PAR_NO_GUIDE_FILE_CPF "crc"
# Implmentation : View/Edit Placed Design (Floorplanner)
crc.mfp
# Implementation : Guide Results Report
crc_summary.html
# Implmentation : Guide Results Report
__projnav/nc1TOncd_tcl.rsp
crc.ncd
crc.par
crc.pad
crc_pad.txt
crc_pad.csv
crc.pad_txt
crc.dly
reportgen.log
crc.xpi
crc.grf
crc.itr
crc_last_par.ncd
crc.placed_ncd_tracker
crc.routed_ncd_tracker
crc.cmd_log
PAR_NO_GUIDE_FILE_CPF "crc"
# Asynchronous Delay Report
crc.dly
reportgen.log
# Generate Programming File
__projnav/crc_ncdTOut_tcl.rsp
__projnav/bitgen.rsp
bitgen.ut
crc.ut
# Generate Programming File
crc.bgn
crc.rbt
crc.ll
crc.msk
crc.drc
crc.nky
crc.bit
crc.bin
crc.isc
crc.cmd_log
# Generate PROM, ACE, or JTAG File
crc.ace
xilinx.sys
crc.mpm
crc.mcs
crc.prm
crc.dst
crc.exo
crc.tek
crc.hex
crc.svf
crc.stapl
impact.cmd
_impact.log
_impact.cmd
# xst flow : RunXST
crc_summary.html
# XST (Creating Lso File) : 
crc.lso
# xst flow : RunXST
crc_summary.html
# xst flow : RunXST
crc.syr
crc.prj
crc.sprj
crc.ana
crc.stx
crc.cmd_log
tipod.ngc
crc.ngc
tipod.ngr
crc.ngr
# Implmentation : Translate
__projnav/ednTOngd_tcl.rsp
"c:\documents and settings\administrador\mis documentos\teleco files\4 teleco\1er cuatrimestre\arquitectura de computadores [9][ac]\practicas\practica 1 generador crc/_ngo"
crc.ngd
crc_ngdbuild.nav
crc.bld
.untf
crc.cmd_log
# Implementation : Map
crc_summary.html
# Implementation : Map
crc_map.ncd
crc.ngm
crc.pcf
crc.nc1
crc.mrp
crc_map.mrp
crc.mdf
crc.cmd_log
MAP_NO_GUIDE_FILE_CPF "crc"
crc_map.ngm
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
crc.twr
crc.twx
crc.tsi
crc.cmd_log
# Implementation : Place & Route
crc_summary.html
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
crc.ncd
crc.par
crc.pad
crc_pad.txt
crc_pad.csv
crc.pad_txt
crc.dly
reportgen.log
crc.xpi
crc.grf
crc.itr
crc_last_par.ncd
crc.placed_ncd_tracker
crc.routed_ncd_tracker
crc.cmd_log
PAR_NO_GUIDE_FILE_CPF "crc"
# Implementation : Generate Post-Synthesis Simulation Model
crc_synthesis.vhd
crc_synthesis.nlf
crc.vhdsim_synth
crc.synth_nlf
crc.cmd_log
crc_synthesis.vhd
# View RTL Schematic
crc.ngr
crc.ngc
# View Technology Schematic
crc.ngr
crc.ngc
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