clk_div3.gfl

vhdl语言写的基数分频器

# XST (Creating Lso File) : 
clk_div3.lso
# xst flow : RunXST
clk_div3.syr
clk_div3.prj
clk_div3.sprj
clk_div3.ana
clk_div3.stx
clk_div3.cmd_log
# XST (Creating Lso File) : 
clk_div3.lso
# xst flow : RunXST
clk_div3.syr
clk_div3.prj
clk_div3.sprj
clk_div3.ana
clk_div3.stx
clk_div3.cmd_log
# XST (Creating Lso File) : 
clk_div3.lso
# xst flow : RunXST
clk_div3.syr
clk_div3.prj
clk_div3.sprj
clk_div3.ana
clk_div3.stx
clk_div3.cmd_log
# XST (Creating Lso File) : 
clk_div3.lso
# xst flow : RunXST
clk_div3.syr
clk_div3.prj
clk_div3.sprj
clk_div3.ana
clk_div3.stx
clk_div3.cmd_log
# XST (Creating Lso File) : 
clk_div3.lso
# xst flow : RunXST
clk_div3.syr
clk_div3.prj
clk_div3.sprj
clk_div3.ana
clk_div3.stx
clk_div3.cmd_log
# XST (Creating Lso File) : 
clk_div3.lso
# xst flow : RunXST
clk_div3.syr
clk_div3.prj
clk_div3.sprj
clk_div3.ana
clk_div3.stx
clk_div3.cmd_log
clk_div3.ngc
clk_div3.ngr
# XST (Creating Lso File) : 
clk_div3.lso
# xst flow : RunXST
clk_div3.syr
clk_div3.prj
clk_div3.sprj
clk_div3.ana
clk_div3.stx
clk_div3.cmd_log
clk_div3.ngc
clk_div3.ngr
# ProjNav -> New Source -> TBW
F:\clk_div3\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
clk_div3_tbw.vhw
clk_div3_tbw.ano
clk_div3_tbw.tfw
# ModelSim : Simulate Behavioral VHDL Model
clk_div3_tbw.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
clk_div3_tbw.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)