代码搜索：shift

找到约 10,000 项符合「shift」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
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srm tx_shift.srm

@E"VRMNFMl;C"RHyVDjCR "VR8G:\HMDHGb\#H\_0#_bHODFFsMkMCPs_C\sdO_D o3CMPR";yDVHC R4V8R":H\GDGHM\H#b_#0\bOH_FsFDkCMMsC_PsOd\F0kMCcs_L3H0PR";yDVHC R.V8R":H\GDGHM\H#b_#0\bOH_FsFDkCMMsC_PsOd\F0kMC6s_L3H0
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plg tx_shift.plg

@P: Worst Slack : NA @P: spi_master_interface_bt_top_tb Part : xc2v40cs144-6 @P: spi_master_interface_bt_top_tb I/O Register bits : 0 @P: spi_master_interface_bt_top_tb Register bits (Non I/O) : 0
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fse tx_shift.fse

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tlg tx_shift.tlg

Selecting top level module spi_master_interface_bt_top_tb Synthesizing module mcu_interface @N: CL201 :"D:\Xilinx\spi_t\spi_coolrunner_ver3\mcu_interface.v":125:3:125:8|Trying to extract state machi
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srs tx_shift.srs

# # # # Created by Synplify Verilog HDL Compiler version Compilers 2.6.0, Build 102R from Synplicity, Inc. # Copyright 1994-1999 Synplicity, Inc. , All rights reserved. # Synthesis Netlist writte
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srd tx_shift.srd

f "noname"; #file 0 f "d:\xilinx\spi_t\spi_coolrunner_ver3\clk_gen.v"; #file 1 f "d:\xilinx\spi_t\spi_coolrunner_ver3\counter_4bit.v"; #file 2 f "d:\xilinx\spi_t\spi_coolrunner_ver3\counter_5bit.v"
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ncf tx_shift.ncf

# # Constraints generated by Synplify Pro 7.3.5, Build 256R # # Period Constraints #Begin clock constraints #End clock constraints # Output Constraints # Input Constraints # Location C
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srr tx_shift.srr

$ Start of Compile #Tue Mar 18 22:40:32 2008 Synplicity Verilog Compiler, version Compilers 2.6.0, Build 102R, built Jan 27 2004 Copyright (C) 1994-2004, Synplicity Inc. All Rights Reserved @
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vwf shift16.vwf

/* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to
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pin shift16.pin

-- Copyright (C) 1991-2005 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions,
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