tx_shift.tlg

a verilog prigram for SPI

Selecting top level module spi_master_interface_bt_top_tb
Synthesizing module mcu_interface
@N: CL201 :"D:\Xilinx\spi_t\spi_coolrunner_ver3\mcu_interface.v":125:3:125:8|Trying to extract state machine for register state
Extracted state machine for register state
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
Synthesizing module state_controller
@N: CL201 :"D:\Xilinx\spi_t\spi_coolrunner_ver3\state_controller.v":166:3:166:8|Trying to extract state machine for register address
Extracted state machine for register address
State machine has 4 reachable states with original encodings of:
   001
   010
   011
   100
@N: CL201 :"D:\Xilinx\spi_t\spi_coolrunner_ver3\state_controller.v":81:3:81:8|Trying to extract state machine for register state
Extracted state machine for register state
State machine has 13 reachable states with original encodings of:
   0000
   0001
   0010
   0011
   0100
   0101
   0110
   0111
   1000
   1001
   1010
   1011
   1100
Synthesizing module state_controller_top
Synthesizing module counter_5bit
Synthesizing module clk_gen
Synthesizing module tx_shift
Synthesizing module rec_shift
@W: CL170 :"D:\Xilinx\spi_t\spi_coolrunner_ver3\rec_shift.v":41:3:41:8|Pruning bit <7> of data_int[7:0] - not in use ...

Synthesizing module counter_4bit
Synthesizing module spi_controller
@W: CL118 :"D:\Xilinx\spi_t\spi_coolrunner_ver3\spi_controller.v":116:9:116:12|Latch generated from always block for signal next_state[3:0], probably caused by a missing assignment in an if or case stmt
Synthesizing module spi_interface
Synthesizing module spi_master
Synthesizing module spi_master_interface
@N: CL201 :"D:\Xilinx\spi_t\spi_coolrunner_ver3\spi_master_interface.v":32:3:32:8|Trying to extract state machine for register state
Extracted state machine for register state
State machine has 8 reachable states with original encodings of:
   000
   001
   010
   011
   100
   101
   110
   111
Synthesizing module spi_master_interface_bt
@N: CL201 :"D:\Xilinx\spi_t\spi_coolrunner_ver3\spi_master_interface_bt.v":31:3:31:8|Trying to extract state machine for register state
Extracted state machine for register state
State machine has 9 reachable states with original encodings of:
   0000
   0001
   0010
   0011
   0100
   0101
   0110
   0111
   1000
Synthesizing module spi_master_interface_bt_top
Synthesizing module spi_master_interface_bt_top_tb
@W: CG293 :"D:\Xilinx\spi_t\spi_coolrunner_ver3\spi_master_interface_bt_top_tb.v":9:3:9:9|Ignoring initial statement
@W: CG293 :"D:\Xilinx\spi_t\spi_coolrunner_ver3\spi_master_interface_bt_top_tb.v":15:3:15:9|Ignoring initial statement
@W: CG133 :"D:\Xilinx\spi_t\spi_coolrunner_ver3\spi_master_interface_bt_top_tb.v":3:7:3:9|No assignment to clk
@W: CG133 :"D:\Xilinx\spi_t\spi_coolrunner_ver3\spi_master_interface_bt_top_tb.v":3:11:3:15|No assignment to reset
@W: CL168 :"D:\Xilinx\spi_t\spi_coolrunner_ver3\spi_master_interface_bt_top_tb.v":23:31:23:41|Pruning instance spi_int_top - not in use ...