tx_shift.srr

a verilog prigram for SPI

$ Start of Compile
#Tue Mar 18 22:40:32 2008

Synplicity Verilog Compiler, version Compilers 2.6.0, Build 102R, built Jan 27 2004
Copyright (C) 1994-2004, Synplicity Inc.  All Rights Reserved

@I::"D:\Xilinx\spi_t\spi_coolrunner_ver3\clk_gen.v"
@I::"D:\Xilinx\spi_t\spi_coolrunner_ver3\counter_4bit.v"
@I::"D:\Xilinx\spi_t\spi_coolrunner_ver3\counter_5bit.v"
@I::"D:\Xilinx\spi_t\spi_coolrunner_ver3\mcu_interface.v"
@I::"D:\Xilinx\spi_t\spi_coolrunner_ver3\rec_shift.v"
@I::"D:\Xilinx\spi_t\spi_coolrunner_ver3\spi_controller.v"
@I::"D:\Xilinx\spi_t\spi_coolrunner_ver3\spi_interface.v"
@I::"D:\Xilinx\spi_t\spi_coolrunner_ver3\spi_master.v"
@I::"D:\Xilinx\spi_t\spi_coolrunner_ver3\spi_master_interface.v"
@I::"D:\Xilinx\spi_t\spi_coolrunner_ver3\spi_master_interface_bt.v"
@I::"D:\Xilinx\spi_t\spi_coolrunner_ver3\spi_master_interface_bt_top.v"
@I::"D:\Xilinx\spi_t\spi_coolrunner_ver3\spi_master_interface_bt_top_tb.v"
@I::"D:\Xilinx\spi_t\spi_coolrunner_ver3\state_controller.v"
@I::"D:\Xilinx\spi_t\spi_coolrunner_ver3\state_controller_top.v"
@I::"D:\Xilinx\spi_t\spi_coolrunner_ver3\tx_shift.v"
Verilog syntax check successful!

Compiler output is up to date.  No re-compile necessary

Selecting top level module spi_master_interface_bt_top_tb
Synthesizing module mcu_interface
@N: CL201 :"D:\Xilinx\spi_t\spi_coolrunner_ver3\mcu_interface.v":125:3:125:8|Trying to extract state machine for register state
Extracted state machine for register state
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
Synthesizing module state_controller
@N: CL201 :"D:\Xilinx\spi_t\spi_coolrunner_ver3\state_controller.v":166:3:166:8|Trying to extract state machine for register address
Extracted state machine for register address
State machine has 4 reachable states with original encodings of:
   001
   010
   011
   100
@N: CL201 :"D:\Xilinx\spi_t\spi_coolrunner_ver3\state_controller.v":81:3:81:8|Trying to extract state machine for register state
Extracted state machine for register state
State machine has 13 reachable states with original encodings of:
   0000
   0001
   0010
   0011
   0100
   0101
   0110
   0111
   1000
   1001
   1010
   1011
   1100
Synthesizing module state_controller_top
Synthesizing module counter_5bit
Synthesizing module clk_gen
Synthesizing module tx_shift
Synthesizing module rec_shift
@W: CL170 :"D:\Xilinx\spi_t\spi_coolrunner_ver3\rec_shift.v":41:3:41:8|Pruning bit <7> of data_int[7:0] - not in use ...

Synthesizing module counter_4bit
Synthesizing module spi_controller
@W: CL118 :"D:\Xilinx\spi_t\spi_coolrunner_ver3\spi_controller.v":116:9:116:12|Latch generated from always block for signal next_state[3:0], probably caused by a missing assignment in an if or case stmt
Synthesizing module spi_interface
Synthesizing module spi_master
Synthesizing module spi_master_interface
@N: CL201 :"D:\Xilinx\spi_t\spi_coolrunner_ver3\spi_master_interface.v":32:3:32:8|Trying to extract state machine for register state
Extracted state machine for register state
State machine has 8 reachable states with original encodings of:
   000
   001
   010
   011
   100
   101
   110
   111
Synthesizing module spi_master_interface_bt
@N: CL201 :"D:\Xilinx\spi_t\spi_coolrunner_ver3\spi_master_interface_bt.v":31:3:31:8|Trying to extract state machine for register state
Extracted state machine for register state
State machine has 9 reachable states with original encodings of:
   0000
   0001
   0010
   0011
   0100
   0101
   0110
   0111
   1000
Synthesizing module spi_master_interface_bt_top
Synthesizing module spi_master_interface_bt_top_tb
@W: CG293 :"D:\Xilinx\spi_t\spi_coolrunner_ver3\spi_master_interface_bt_top_tb.v":9:3:9:9|Ignoring initial statement
@W: CG293 :"D:\Xilinx\spi_t\spi_coolrunner_ver3\spi_master_interface_bt_top_tb.v":15:3:15:9|Ignoring initial statement
@W: CG133 :"D:\Xilinx\spi_t\spi_coolrunner_ver3\spi_master_interface_bt_top_tb.v":3:7:3:9|No assignment to clk
@W: CG133 :"D:\Xilinx\spi_t\spi_coolrunner_ver3\spi_master_interface_bt_top_tb.v":3:11:3:15|No assignment to reset
@W: CL168 :"D:\Xilinx\spi_t\spi_coolrunner_ver3\spi_master_interface_bt_top_tb.v":23:31:23:41|Pruning instance spi_int_top - not in use ...

@END
Process took 0h:0m:0s realtime, 0h:0m:0s cputime
###########################################################[
Synplicity Xilinx Technology Mapper, version 7.3.5, Build 256R, built Mar 25 2004
Copyright (C) 1994-2004, Synplicity Inc.  All Rights Reserved


@N: MT210 |Because the design is Purely Combinational, Autoconstrain mode is TURNED OFF
Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
------------------------------------------------------------

Net buffering Report for view:work.spi_master_interface_bt_top_tb(verilog):
No nets needed buffering.

@N: FX164 |The option to pack flops in the IOB has not been specified 
Writing Analyst data base D:\Xilinx\spi_t\spi_coolrunner_ver3\rev_1\tx_shift.srm
Writing EDIF Netlist and constraint files


##### START OF TIMING REPORT #####[
# Timing Report written on Tue Mar 18 22:40:40 2008
#


Top view:               spi_master_interface_bt_top_tb
Requested Frequency:    1.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N: MT195 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..

@N: MT197 |Clock constraints cover only FF-to-FF paths associated with the clock..



Performance Summary 
*******************


Worst slack in design: NA






Interface Information 
*********************

		No IO constraint found 


##### END OF TIMING REPORT #####]


---------------------------------------
Resource Usage Report for spi_master_interface_bt_top_tb 

Mapping to part: xc2v40cs144-6
I/O Register bits:                  0
Register bits not including I/Os:   0 (0%)

Mapping Summary:
Total  LUTs: 0 (0%)

Mapper successful!
Process took 0h:0m:4s realtime, 0h:0m:4s cputime
###########################################################]