代码搜索：shift
找到约 10,000 项符合「shift」的源代码
代码结果 10,000
www.eeworm.com/read/482889/1283772
hpp shift_op.hpp
// NO INCLUDE GUARDS, THE HEADER IS INTENDED FOR MULTIPLE INCLUSION
// Copyright Aleksey Gurtovoy 2000-2004
//
// Distributed under the Boost Software License, Version 1.0.
// (See accompanyi
www.eeworm.com/read/482889/1283996
hpp shift_left.hpp
#ifndef BOOST_MPL_SHIFT_LEFT_HPP_INCLUDED
#define BOOST_MPL_SHIFT_LEFT_HPP_INCLUDED
// Copyright Aleksey Gurtovoy 2000-2004
// Copyright Jaap Suter 2003
//
// Distributed under the Boost Soft
www.eeworm.com/read/477111/1364267
m sig_shift.m
function [yshift,n]=sig_shift(x,m,n0)
%信号延迟的程序，m为输入x的下标
%n0为延迟的单位长度
n=m+n0;
yshift=x;
function [yam,n]=sig_proc(x1,n1,x2,n2,s)
%信号相加和相乘的程序
%x1，x2分别为输入序列，n1，n2为对应下标
%s=0为加法；其他值为乘法
n=min(min(
www.eeworm.com/read/476527/1368722
vhd reg_shift.vhd
--** 移位寄存器 **--
--文件名：reg_shift.vhd
--功 能：移位寄存器
--说 明：“data”采用八位拨盘开关来置入数据；
-- “q”中的数据每秒中移动一次，采用发光二极管来表示；
-- “enable”作为数据的输入使
www.eeworm.com/read/476527/1368723
ucf reg_shift.ucf
NET "cs" LOC = "p175";
NET "cs" LOC = "p176";
NET "datain" LOC = "p110";
NET "datain" LOC = "p111";
NET "datain" LOC = "p112";
NET "datain" LOC = "p113";
NET "datain
www.eeworm.com/read/470693/1467493
cc bitset_shift.cc
// 2000-01-15 Anders Widell
// Copyright (C) 2000 Free Software Foundation, Inc.
//
// This file is part of the GNU ISO C++ Library. This library is free
// software; you can
www.eeworm.com/read/470676/1467771
vhd shift_reg.vhd
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY dff IS
PORT (d : IN std_logic;
clk : IN std_logic;
q : OUT std_logic);
END dff;
ARCHITECTURE rtl OF
www.eeworm.com/read/470676/1467780
vhd shift_reg.vhd
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY dff IS
PORT (d : IN std_logic;
clk : IN std_logic;
q : OUT std_logic);
END dff;
ARCHITECTURE rtl OF
www.eeworm.com/read/470676/1467781
vhd shift_reg.vhd
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY dff IS
PORT (d : IN std_logic;
clk : IN std_logic;
q : OUT std_logic);
END dff;
ARCHITECTURE rtl OF
www.eeworm.com/read/470676/1467801
vhd shift_regn.vhd
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY dff IS
PORT (d : IN std_logic;
clk : IN std_logic;
q : OUT std_logic);
END dff;
ARCHITECTURE rtl OF