shift_reg.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY dff IS
       PORT (d   : IN  std_logic;
             clk : IN  std_logic;
             q   : OUT std_logic);
END dff;

ARCHITECTURE rtl OF dff IS
BEGIN
     PROCESS (clk)
     BEGIN
          IF (clk'event AND clk = '1') THEN
              q <= d;
          END IF;
     END PROCESS;
END rtl;

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
--USE WORK.example.ALL;

ENTITY shift_reg IS 
           PORT (d1  : IN  std_logic;
                 cp  : IN  std_logic;
		 d0  : OUT std_logic);
END shift_reg;

ARCHITECTURE structure OF shift_reg IS
         COMPONENT dff
            PORT (d   : IN  std_logic;
                  clk : IN  std_logic;
		  q   : OUT std_logic);
         END COMPONENT;
         SIGNAL  q   : std_logic_vector(3 DOWNTO 1);
BEGIN
     G1:FOR i IN 0 TO 3 GENERATE
         P1:IF (i = 0) GENERATE
             dffx: dff  PORT MAP (d1,cp,q(i+1));
         END GENERATE P1;

         P2:IF (i = 3) GENERATE
             dffx: dff  PORT MAP (q(i),cp,d0);
         END GENERATE P2;

         P3:IF ((i /= 0) AND (i /= 3)) GENERATE
             dffx: dff  PORT MAP (q(i),cp,q(i+1));
         END GENERATE P3;
     END GENERATE G1;
END structure;