shift_reg.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY dff IS
       PORT (d   : IN  std_logic;
             clk : IN  std_logic;
             q   : OUT std_logic);
END dff;

ARCHITECTURE rtl OF dff IS
BEGIN
     PROCESS (clk)
     BEGIN
          IF (clk'event AND clk = '1') THEN
              q <= d;
          END IF;
     END PROCESS;
END rtl;

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
--USE WORK.example.ALL;

ENTITY shift_reg IS 
           PORT (d1  : IN  std_logic;
                 cp  : IN  std_logic;
		 d0  : OUT std_logic);
END shift_reg;

ARCHITECTURE structure OF shift_reg IS
         COMPONENT dff
            PORT (d   : IN  std_logic;
                  clk : IN  std_logic;
		  q   : OUT std_logic);
         END COMPONENT;
         SIGNAL  q   : std_logic_vector(4 DOWNTO 0);
BEGIN
         q(0) <= d1;
	 dff1: dff  PORT MAP (q(0),cp,q(1));
	 dff2: dff  PORT MAP (q(1),cp,q(2));
	 dff3: dff  PORT MAP (q(2),cp,q(3));
         dff4: dff  PORT MAP (q(3),cp,q(4));
         d0 <= q(4);
END structure;