代码搜索：proasic3
找到约 74 项符合「proasic3」的源代码
代码结果 74
www.eeworm.com/read/18679/799626
pdf proasic3 startkit原理图.pdf
www.eeworm.com/read/471689/6888133
do run.do
quietly set ACTELLIBNAME proasic3
quietly set PROJECT_DIR "C:/Documents and Settings/BySky/My Documents/4bitcomp"
if {[file exists presynth/_info]} {
puts "INFO: Simulation library presynth al
www.eeworm.com/read/424889/10403117
ini modelsim.ini
[Library]
others = $MODEL_TECH/../modelsim.ini
proasic3 = $MODEL_TECH/../actel/vlog/proasic3
syncad_vhdl_lib = E:\Libero\Designer/lib/actel/syncad_vhdl_lib
[vcom]
VHDL93 = 1
www.eeworm.com/read/424889/10403125
sav modelsim.ini.sav
[Library]
others = $MODEL_TECH/../modelsim.ini
proasic3 = $MODEL_TECH/../actel/vlog/proasic3
syncad_vhdl_lib = D:\Actel\Libero7.3\Designer/lib/actel/syncad_vhdl_lib
[vcom]
VHD
www.eeworm.com/read/430277/6290771
ini modelsim.ini
[Library]
others = $MODEL_TECH/../modelsim.ini
proasic3 = D:/Libero/Designer/lib/modelsim/precompiled/vlog/proasic3
syncad_vhdl_lib = D:\Libero\Designe
www.eeworm.com/read/430277/6290772
sav modelsim.ini.sav
[Library]
others = $MODEL_TECH/../modelsim.ini
proasic3 = D:/Libero/Designer/lib/modelsim/precompiled/vlog/proasic3
syncad_vhdl_lib = D:\Libero\Designer/
www.eeworm.com/read/471689/6888115
ini modelsim.ini
[Library]
others = $MODEL_TECH/../modelsim.ini
proasic3 = C:/Libero/Designer/lib/modelsim/precompiled/vhdl/proasic3
syncad_vhdl_lib = C:\Libero\Designer/lib/actel/syncad_vhdl_lib
presynth = pres
www.eeworm.com/read/140841/5779841
vhd tech.vhd
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free so
www.eeworm.com/read/315669/13538564
log stdout.log
Starting: C:\Libero\Synplify\Synplify_88A1\bin\mbin\synplify.exe
Install: C:\Libero\Synplify\Synplify_88A1
Date: Wed May 21 14:37:47 2008
Version: 8.8A1
Arguments: cmos_f
www.eeworm.com/read/18154/777235
do run.do
quietly set ACTELLIBNAME proasic3
quietly set PROJECT_DIR "H:/fpga_test/fpga_fifo_0122_02"
vlib presynth
vmap proasic3 "$env(MODEL_TECH)/../actel/vlog/proasic3"
vmap presynth presynth
vlog "+incd