modelsim.ini

主芯片：Actel的FPGA030,Verilog语言,串口发送和接收的例程

[Library]
others = $MODEL_TECH/../modelsim.ini
proasic3 = D:/Libero/Designer/lib/modelsim/precompiled/vlog/proasic3























syncad_vhdl_lib = D:\Libero\Designer/lib/actel/syncad_vhdl_lib

[vcom]
VHDL93 = 1

[vsim]
IterationLimit = 5000