代码搜索：practice
找到约 1,173 项符合「practice」的源代码
代码结果 1,173
www.eeworm.com/read/217949/14942633
m set_z0.m
function Set_Z0(z0)
%
% this function sets a global variable Z0 which is
% used for Smith Chart computations
%
% USAGE: Set_Z0(50)
% |
% +---- Sets characterist
www.eeworm.com/read/217949/14942635
m s_point.m
function s_Point(Z)
%
% This function plots a point on the Smith Chart
% It is assume that global variable Z0 has
% already been set (see Set_Z0)
%
% usage: s_Point(30+j*20)
%
% Copyright (
www.eeworm.com/read/214502/15098359
drc song.drc
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net carry is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the fli
www.eeworm.com/read/210234/15203124
drc pingche.drc
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net XLXN_25 is sourced by
a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the f
www.eeworm.com/read/210233/15203339
drc qd.drc
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net XLXI_10__n0001 is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data int
www.eeworm.com/read/210233/15203456
drc qdkz.drc
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net XLXI_8__n0010 is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into
www.eeworm.com/read/210228/15203972
drc ps2_lcd1602_1.drc
WARNING:PhysDesignRules:372 - Gated clock. Clock net a0/_n0017 is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-
www.eeworm.com/read/208361/15248252
drc lz.drc
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net XLXI_5__n0001 is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into
www.eeworm.com/read/208258/15250030
drc jtd.drc
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net SF668 is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the fli
www.eeworm.com/read/208258/15250057
drc jt.drc
WARNING:PhysDesignRules:372 - Gated clock. Clock net XLXI_4__n0021 is sourced by
a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the f